Method of manufacturing a contact element and a multi-layered wiring substrate, and wafer batch contact board

• US 20010019177A1
• Filed: 12/27/2000
• Published: 09/06/2001
• Est. Priority Date: 12/27/1999
• Status: Active Grant

• Current Assignee: Hoya Corporation
• Original Assignee: Hoya Corporation
• Inventors: Sugihara, Osamu
• Granted Patent: US 6,406,991 B2
• Time in Patent Office: Days
• US Class Current: 257/780
• CPC Class Codes: F28F 2265/26 for allowing differential expansion between elements floating header box elements F28F9/0236
• CPC Class Codes: F28F 9/001 Casings in the form of plate-like arrangements; Frames enclosing a heat exchange core
• CPC Class Codes: G01R 1/06761 related to layers
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H05K 2201/0154 Polyimide
• CPC Class Codes: H05K 2201/0367 Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/0394 Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2203/0733 Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 2203/095 Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
• CPC Class Codes: H05K 3/0035 of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/0055 After-treatment, e.g. cleaning or desmearing of holes
• CPC Class Codes: H05K 3/381 by special treatment of the substrate
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/4007 Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/423 characterised by electroplating method
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/467 Adding a circuit layer by thin film methods H05K3/4647 takes precedence
• CPC Class Codes: Y10S 438/906 : Cleaning of wafer as interim step
• CPC Class Codes: Y10S 438/963 : Removing process residues from vertical substrate surfaces
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

In a method of manufacturing a contact element, provision is made of a laminated body which has an insulating film, an electrically conductive layer stacked on the insulating film, and bump holes opened. A treatment is carried out so as to remove organic materials and the like from an interior of the bump holes and/or a surface of the insulating film before bumps are formed on the bump holes. The treatment may be a plasma treatment or an X-ray irradiation.

Claims

1. A method for manufacturing a contact element, comprising the steps of:

forming a laminated body including an insulating film and at least one electrically conductive layer;

forming, in the predetermined positions of the insulating film, bump holes extending from the surface of the insulating film to the at least one electrically conductive layer;

performing surface treatment by carrying out a plasma treatment to treat the interior of the bump holes and/or the surface of the insulating film; and

forming bumps on the bump holes treated in the surface treatment step.

3. A method for manufacturing a contact element according to

claim 1

, wherein the bump holes are formed through a laser treatment.

4. A method for manufacturing a contact element according to

claim 1

, wherein

after the surface treatment performed by carrying out the plasma treatment to treat the interior of the bump holes and/or the surface of the insulating film, an oxide film removal treatment is carried out prior to an electrolytic plating or a non-electrolytic plating, for removing an oxide film of an electrically conductive layer exposed to the bottoms of the bump holes, and followed by forming bumps on the bump holes through the electrolytic plating, with the electrically conductive layer serving as an electrode.

5. A method for manufacturing a contact element according to

claim 1

, further comprising a step of spreading the laminated body over a support frame.

9. A wafer batch contact board comprising:

a contact element for use in a wafer batch contact board which is produced according to the method of

claim 5

;

a multi-layered wiring substrate for use in a wafer batch contact board which is produced according to the method of

claim 8

; and

an anisotropic electrically conductive rubber for electrically connecting the multi-layered wiring substrate with the contact element.

2. A method for manufacturing a contact element, comprising the steps of:

forming a laminated body including an insulating film and at least one electrically conductive layer;

forming, in the predetermined positions of the insulating film, bump holes extending from the surface of the insulating film to the at least one electrically conductive layer;

performing surface treatment by carrying out an X-ray irradiation to treat the interior of the bump holes and/or the surface of the insulating film; and

forming bumps on the bump holes treated in the surface treatment step.

10. A method for manufacturing a contact element according to

claim 2

, wherein the bump holes are formed through a laser treatment.

11. A method for manufacturing a contact element according to

claim 2

, wherein

after the surface treatment performed by carrying out the X-ray irradiation to treat the interior of the bump holes and/or the surface of the insulating film, an oxide film removal treatment is carried out prior to an electrolytic plating or a non-electrolytic plating, for removing an oxide film of an electrically conductive layer exposed to the bottoms of the bump holes, and followed by forming bumps on the bump holes through the electrolytic plating, with the electrically conductive layer serving as an electrode.

12. A method for manufacturing a contact element according to

claim 2

, further comprising a step of spreading the laminated body over a support frame.

14. A wafer batch contact board comprising:

a contact element for use in a wafer batch contact board which is produced according to the method of

claim 12

;

a multi-layered wiring substrate for use in a wafer batch contact board which is produced according to the method of

claim 13

; and

an anisotropic electrically conductive rubber for electrically connecting the multi-layered wiring substrate with the contact element.

6. A method for manufacturing a multi-layered wiring substrate which is formed by at first laminating, on an insulating substrate material, a plurality of electrically conductive layers with an insulating layer interposed therebetween, then conducting the electrically conductive layers through a plurality of contact holes formed in the insulating layer, the method comprising:

a surface treatment which is effected by carrying out a plasma treatment to treat the interior of the contact holes and/or the surface of the insulating layer, in an atmosphere of a mixed gas formed by an oxygen gas and another gas containing halogen atoms in its molecules.

8. A method according to

claim 6

, for manufacturing a multi-layered wiring substrate forming part of a wafer batch contact board which is for use in the batch examining of numerous semiconductor devices formed on a wafer, the method comprising the steps of:

forming a first electrically conductive layer on an insulating substrate, patterning the first electrically conductive layer to form a first wiring pattern;

forming an insulating layer on the first wiring pattern and forming contact holes in the insulating layer;

performing a surface treatment which is effected by carrying out the plasma treatment or the X-ray irradiation to treat the interior of the contact holes and/or the surface of the insulating layer; and

forming a second electrically conductive layer on an insulating substrate, patterning the second electrically conductive layer to form a second wiring pattern;

wherein a series of processes including the step of forming the insulating film and the contact holes, the step of performing the surface treatment and the step of forming the second wiring pattern are repeated at least once.

7. A method for manufacturing a multi-layered wiring substrate which is formed by at first laminating, on an insulating substrate material, a plurality of electrically conductive layers with an insulating layer interposed therebetween, then conducting the electrically conductive layers through a plurality of contact holes formed in the insulating layer, the method comprising:

a surface treatment which is effected by carrying out an X-ray irradiation to treat the interior of the contact holes and/or the surface of the insulating layer.

13. A method according to

claim 7

, for manufacturing a multi-layered wiring substrate forming part of a wafer batch contact board which is for use in the batch examining of numerous semiconductor devices formed on a wafer, the method comprising the steps of:

forming a first electrically conductive layer on an insulating substrate, patterning the first electrically conductive layer to form a first wiring pattern;

forming an insulating layer on the first wiring pattern and forming contact holes in the insulating layer;

performing a surface treatment which is effected by carrying out the plasma treatment or the X-ray irradiation to treat the interior of the contact holes and/or the surface of the insulating layer; and

forming a second electrically conductive layer on an insulating substrate, patterning the second electrically conductive layer to form a second wiring pattern;

wherein a series of processes including the step of forming the insulating film and the contact holes, the step of performing the surface treatment and the step of forming the second wiring pattern are repeated at least once.