Waveform generator and testing device

• US 20010019313A1
• Filed: 03/09/2001
• Published: 09/06/2001
• Est. Priority Date: 07/12/1999
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Takahashi, Takeshi, Furukawa, Yasuo, Kawabata, Masayuki
• Granted Patent: US 6,404,371 B2
• Time in Patent Office: Days
• US Class Current: 341/147
• CPC Class Codes: G01R 31/2841 Signal generators
• CPC Class Codes: G06F 1/022 Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers G06F1/025, G06F1/03 take precedence

Abstract

A waveform generator 30 for generating a desired waveform includes a plurality of rectangular wave generators (40a to 40n) for generating a plurality of rectangular waves and a waveform synthesizing unit 42 for synthesizing the rectangular waves to generate a multi-level synthesized wave, and generate the desired wave based on the synthesized wave.

Claims

1. A waveform generator for generating a desired waveform comprising:

a rectangular wave generating unit operable to generate a plurality of rectangular waves; and

a waveform synthesizing unit operable to synthesize said plurality of rectangular waves to generate a multi-level synthesized wave, wherein said desired waveform is generated based on said synthesized wave.

2. A waveform generator as claimed in

claim 1

, wherein said rectangular wave generating unit generates said plurality of rectangular waves in such a manner that each of said plurality of rectangular waves rises at a desired rising timing based on said desired waveform and falls at a desired falling timing based on said desired waveform.

3. A waveform generator as claimed in

claim 1

or

2

, further comprising a filter operable to remove a predetermined frequency component from said synthesized wave.

4. A waveform generator as claimed in of any one of

claims 1

to

3

, wherein said rectangular wave generating unit includes a waveform memory operable to store information regarding a voltage value of each of said plurality of rectangular waves.

5. A waveform generator as claimed in any one of

claims 2

to

4

, wherein said rectangular wave generating unit further includes:

a timing memory operable to store said rising timing and said falling timing of each of said plurality of rectangular waves; and

a rectangular wave outputting unit operable to output each of said plurality of rectangular waves based on said information and said timing of each of said rectangular waves.

6. A waveform generator as claimed in any one of

claims 2

to

4

, wherein said rectangular wave generating unit includes:

a plurality of waveform memories each operable to store information of a voltage value of a corresponding one of said plurality of rectangular waves;

a plurality of timing memories each operable to store said rising and falling timing of a corresponding one of said plurality of rectangular waves; and

a rectangular wave outputting unit operable to output said rectangular waves based on said information to be out put of each of said rectangular waves and said timing of each of said rectangular waves.

7. A waveform generator as claimed in

claim 5

or

6

, wherein said rectangular wave outputting unit is a D-A converter that converts said information of the voltage value into an analog signal.

8. A waveform generator as claimed in any one of

claims 5

to

7

, further comprising a timing adjuster operable to delay a reference clock based on said timing of each of said rectangular waves stored in said timing memory or each of said timing memories.

9. A waveform generator as claimed in any one of

claims 1

to

8

, further comprising a voltage controller operable to control an amplitude of each of said plurality of rectangular waves based on said desired waveform.

10. A waveform generator as claimed in any one of

claims 1

to

9

, wherein said waveform synthesizing unit performs an operation for the voltage value of each of said plurality of rectangular waves.

11. A waveform generator as claimed in

claim 5

, wherein said rectangular wave generating unit converts said information of the voltage value stored in said waveform memory into an N-digit base-M number (N and M are integers equal to or larger than 2), generates Nth number of logical voltage values that are voltage values specifying logical values corresponding to said N-digit base-M number, and supplies said logical voltage values to said waveform synthesizing unit.

12. A waveform generator as claimed in

claim 11

, wherein said rectangular wave generating unit includes Nth number of rectangular wave generators operable to generate said M-valued logical voltage values, respectively, and

said waveform synthesizing unit multiples, by (1/M)^K times, each of said logical voltage values that is supplied from the K-th waveform generator (K is an integer equal to or larger than 1 but does not exceed N) and synthesizes multipled said logical voltage values so as to generate said desired waveform.

13. A waveform generator as claimed in

claim 12

, wherein said waveform synthesizing unit includes a ladder having said Nth number of logical voltage values as inputs,

said Nth number of rectangular wave generators are electrically connected to Nth number of nodes, respectively,

said nodes are connected to each other via resistors each having a predetermined resistance,

the K-th logical voltage value drops to (1/M) times at the K-th node, and

a voltage value at said K-th node drops to (1/M) times at the (K−

1)th node.

14. A waveform generator as claimed in

claim 12

, wherein said waveform synthesizing unit includes a ladder having said Nth number of logical voltage value as inputs,

the J-th rectangular wave generator (J is an integer equal to or larger than 1 but does not exceed (N−

1)) is connected to (N−

1) nodes,

said nodes are connected to each other via resistors each having a predetermined resistance,

the N-th rectangular wave generator is connected to the (N−

1)th node,

the N-th logical voltage value falls to (1/M) times said N-th logical voltage value at said (N−

1)th node,

the J-th logical voltage value drops to (1/M) times at the J-th node, and

a voltage value at said J-th node drops to (1/M) times at the (J−

1)th node.

15. A testing device for testing an electric device having an A-D converting unit that converts an analog signal to a digital signal, comprising:

a rectangular wave generating unit operable to generate a plurality of rectangular waves;

a waveform synthesizing unit operable to synthesize said plurality of rectangular waves to generate a multi-level synthesized wave; and

a waveform generator operable to generate a testing waveform used for testing said electric device based on said synthesized wave, wherein

said testing waveform is applied to said electrical device so as to test said electric device based on an output value of said electric device to which said testing waveform is applied.

16. A testing device as claimed in

claim 15

, wherein said rectangular wave generating unit generates said plurality of rectangular waves in such a manner that each of said plurality of rectangular waves rises at a desired rising timing based on a desired waveform and falls at a desired falling timing based on a desired waveform.

17. A testing device as claimed in

claim 15

or

16

, further comprising a filter operable to remove a predetermined frequency component from said synthesized wave.

18. A testing device as claimed in

claim 16

, wherein said rectangular wave generating unit converts information of a voltage value of each of said rectangular waves stored in a waveform memory into an N-digit base-M number (N and M are integers equal to or larger than 2), generates Nth number of logical voltage values that are voltage values specifying logical values corresponding to said N-digit base-M number, and supplies said logical voltage values to said waveform synthesizing unit.

19. A testing device as claimed in

claim 18

, wherein said rectangular wave generating unit includes Nth number of rectangular wave generators operable to generate said M-valued logical voltage values, respectively, and

said waveform synthesizing unit multiples, by (1/M)^K times, each of said logical voltage values that is supplied from the K-th waveform generator (K is an integer equal to or larger than 1 but does not exceed N) and synthesizes (1/M)^K times said logical voltage values so as to generate said desired waveform.

20. A testing device as claimed in

claim 19

, wherein said waveform synthesizing unit includes a ladder having said Nth number of logical voltage values as inputs,

said Nth number of rectangular wave generators are electrically connected to Nth number of nodes, respectively,

said nodes are connected to each other via resistors each having a predetermined resistance,

the K-th logical voltage value drops to (1/M) times at the K-th node, and

a voltage value at said K-th node drops to (1/M) times at the (K−

1)th node.

21. A testing device as claimed in

claim 19

, wherein said waveform synthesizing unit includes a ladder having said Nth number of logical voltage value as inputs,

the J-th rectangular wave generator (J is an integer equal to or larger than 1 but does not exceed (N−

1) ) is connected to (N−

1) nodes,

said nodes are connected to each other via resistors each having a predetermined resistance,

the N-th rectangular wave generator is connected to the (N−

1)th node,

the N-th logical voltage value at said (N−

1) th node is (1/M) times said N-th logical voltage value,

the J-th logical voltage value drops to (1/M) times at the J-th node, and

a voltage value at said J-th node drops to (1/M) times at the (J−

1)th node.

22. A testing device as claimed in any one of

claims 18

to

21

, further comprising:

a DC tester operable to conduct a DC test of said electric device;

a selection unit operable to electrically connect one of said DC tester and said rectangular wave generating unit to said waveform synthesizing unit; and

a switching unit operable to switch whether or not said rectangular wave generating unit is electrically connected to said waveform synthesizing unit.

23. A testing device as claimed in

claim 22

, wherein said selection unit electrically connects either said DC tester or one of said rectangular wave generators having the smallest impedance from said electric device to said rectangular wave generator to said waveform synthesizing unit, and

said switching unit switches whether or not others of said rectangular wave generators is electrically connected to said waveform synthesizing unit.

24. A semiconductor device including a testing unit for testing a device unit having an A-D converting unit that converts an analog signal to a digital signal, comprising:

a rectangular wave generating unit operable to generate a plurality of rectangular waves;

a waveform synthesizing unit operable to synthesize said plurality of rectangular waves to generate a synthesized wave;

a waveform generator operable to generate a testing waveform used for testing said A-D converting unit based on said synthesized wave;

said device unit to which said testing waveform is applied; and

said testing unit operable to test said A-D converting unit based on an output value of said device unit to which said testing waveform is applied.

25. A semiconductor device as claimed in

claim 24

, wherein said waveform generating unit generates said plurality of rectangular waves in such a manner each of said rectangular waves rises at a desired rising timing based on a desired waveform and falls at a desired falling timing based on a desired waveform.

26. A semiconductor device as claimed in

claim 24

or

25

, further comprising a filter operable to remove a predetermined frequency component from said synthesized wave.

27. A waveform generation method for generating a desired waveform, comprising the steps of:

generating a plurality of rectangular waves;

synthesizing said plurality of rectangular waves to generate a multi-level synthesized wave; and

generating said desired waveform based on said synthesized wave.

28. A waveform generation method as claimed in

claim 27

, wherein said step of generating said plurality of rectangular waves includes the step of generating said plurality of rectangular waves in such a manner that each of said rectangular waves rises at a desired rising timing based on said desired waveform and falls at a desired falling timing based on said desired waveform.

29. A waveform generation method as claimed in

claim 27

or

28

, wherein said step of generating said multi-level synthesized wave includes the step of calculating voltage values of said plurality of rectangular waves to generate said multi-level synthesized wave.

30. A waveform generation method as claimed in any one of

claims 27

to

29

, further comprising the step of removing a predetermined frequency component of said synthesized wave after said step of generating said multi-level synthesized wave.