Mitigation of substrate defects in reflective reticles using sequential coating and annealing

• US 20010019803A1
• Filed: 03/27/2001
• Published: 09/06/2001
• Est. Priority Date: 12/06/1999
• Status: Active Grant

• Current Assignee: EUV Limited Liability Corporation
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Mirkanimi, Paul B.
• Granted Patent: US 6,489,066 B2
• Time in Patent Office: Days
• US Class Current: 430/5
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G03F 1/24 Reflection masks; Preparation thereof
• CPC Class Codes: G03F 1/38 Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
• CPC Class Codes: G03F 1/72 Repair or correction of mask defects

Abstract

A buffer-layer to minimize the size of defects on a reticle substrate prior to deposition of a reflective coating on the substrate. The buffer-layer is formed by either a multilayer deposited on the substrate or by a plurality of sequentially deposited and annealed coatings deposited on the substrate. The plurality of sequentially deposited and annealed coating may comprise multilayer and single layer coatings. The multilayer deposited and annealed buffer layer coatings may be of the same or different material than the reflecting coating thereafter deposited on the buffer-layer.

Claims

1. In a device for use in lithography having a substrate and a reflective multilayer, the improvement compromising:

a buffer-layer consisting of a plurality of sequentially deposited and annealed layers.

2. The improvement of

claim 1

, wherein said plurality of sequential deposited and annealed layers are composed of material selected from the group consisting of the same material as the reflective multilayer, a material different than that of the reflective multilayer, a combination the same and different materials as in the reflective multilayer.

3. The improvement of

claim 1

, wherein said plurality of sequentially deposited and annealed layers are composed of layers of material selected from the group consisting of multilayer of different material, single material layers, and a combination of multilayer material and single layer material.

4. The improvement of

claim 1

, wherein said buffer-layer has an outer surface roughness of not greater than 0.3 nm.

5. The improvement of

claim 1

, wherein said buffer-layer has a thickness of up to 100 μ

m.

6. The improvement of

claim 1

, wherein said plurality of sequentially deposited and annealed layers are selected from the group consisting of MoSi multilayer films, amorphous silicon films, and combinations of MoSi multilayer and amorphous silicon films.

7. The improvement of

claim 6

, wherein said sequentially deposited layers are annealed at a temperature in the range of 100-600°

C.

8. A reticle for extreme ultraviolet lithography, compromising:

a substrate, and

a buffer-layer,

said buffer-layer consisting of a plurality of sequentially deposited and annealed layers.

9. The reticle of

claim 8

, wherein said plurality of sequentially deposited and annealed layers are composed of a material selected from the group of multilayered material, single layered material, and a combination of multilayered and single layered material.

10. The reticle of

claim 8

, wherein said multilayered material is composed of MoSi, and wherein said single layered material is composed of a-Si.

11. The reticle of

claim 10

, wherein said plurality of sequentially deposited and annealed layers include at least two layers selected from the group consisting of at least two bi-layers of Mo and Si, at least two layers of a-Si, and at least two layers of at least one Mo/Si bilayer and at least one layer of a-Si.

12. The reticle of

claim 11

, wherein each annealed layer of a-Si has a thickness of about 100 nm with a stress of about 500 MPa, and wherein each annealed layer of Mo/Si has a thickness of about 280 nm with a stress of about −

100 MPa.

13. The reticle of

claim 8

, wherein said buffer-layer has an outer surface roughness of no greater than about 0.3 nm.

14. A method for mitigating the effect of substrate particles on reticles, such as utility in extreme ultraviolet lithography, comprising:

providing a buffer-layer on the surface of said substrate having an outer surface roughness of not greater than about 0.3 nm, and

wherein providing the buffer-layer is carried out by sequential coating and annealing of a plurality of layers of material on the substrate.

15. The method of

claim 14

, wherein the effect of substrate particles on reticles of about 25 nm and greater is mitigated by the sequential coating and annealing of the plurality of layers of material on the substrate.

16. The method of

claim 14

, wherein the sequential coating and annealing of the plurality of layers of material is carried out by depositing a first single coating or multilayer coating, annealing the thus deposited first coating, and at least depositing a second single coating or multilayer coating, and annealing the at least second coating.

17. The method of

claim 16

, wherein depositing the multilayer coating is carried out by depositing at least one bilayer of material selected from the group consisting of Mo/Ru/Be and Mo/Be, Mo/Si ion-beam sputtered and deposited to a thickness of up to ˜

100 μ

m.

18. The method of

claim 16

, wherein the annealing is carried out after deposition and at a temperature of about 100-600°

C. for a time period in the range of 0.001-48 hours.

19. The method of

claim 16

, wherein depositing the second layer coating is carried out by depositing a layer of material selected from the group consisting of a-Si, or a-C, and deposited to a thickness of about 100 nm.

20. The method of

claim 16

, wherein the annealing is carried out after depostion and at a temperature I the range of about 100°

C. to about 600°

C. for a time period in the range of 0.001-12 hours per step.

21. The method of

claim 16

, wherein depositing and annealing a single coating is carried out by depositing a 100 nm thick sputtered a-Si coating with a surface roughness of 0.15 nm RMS and a stress of −

1250 MPa, and annealing the thus deposited coating at 300°

C. for about 3 hours, thereby reducing the stress to −

500 MPa with no change in surface roughness.

22. The method of

claim 16

, wherein depositing and annealing a multilayer coating is carried out by depositing a 280 nm thick MoSi multilayer coating with a stress of −

385 MPa, and thereafter annealing at 200°

C. for about 1.5 hours, thereby reducing the stress to −

100 MPa with an after annealed surface roughness of 0.18 nm RMS.