Metallization outside protective overcoat for improved capacitors and inductors

• US 20010019865A1
• Filed: 02/02/2001
• Published: 09/06/2001
• Est. Priority Date: 11/05/1997
• Status: Active Grant

• Current Assignee: John Kenneth Arch, John P. Erdeljac, Khatibzadeh M. Ali, Louis Nicholas Hutter
• Original Assignee: John Kenneth Arch, John P. Erdeljac, Khatibzadeh M. Ali, Louis Nicholas Hutter
• Inventors: Khatibzadeh, M. Ali, Hutter, Louis Nicholas, Arch, John Kenneth, Erdeljac, John P.
• Granted Patent: US 6,284,617 B1
• Time in Patent Office: Days
• US Class Current: 438/239
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.

Claims

1. An integrated circuit structure, comprising:

a first circuit portion enclosed by a protective overcoat with bond pad openings;

an inductor formed of a low resistance material on said protective overcoat.

2. The integrated circuit structure of

claim 1

, wherein said low resistance material is copper.

3. The integrated circuit structure of

claim 1

, wherein said low resistance material is greater than 5 microns thick.

4. An integrated circuit structure, comprising:

a first circuit portion enclosed by a protective overcoat with bond pad openings;

a low-resistance structure which forms one electrode of a capacitor, said low-resistance structure at least partially overlying said protective overcoat.

5. The integrated circuit structure of

claim 4

, wherein said low resistance material is copper.

6. The integrated circuit structure of

claim 4

, wherein said low resistance material is greater than 5 microns thick.

7. An integrated circuit structure, comprising:

a first circuit portion enclosed by a protective overcoat with bond pad openings;

an inductor formed of a low-resistance material, said inductor being outside said protective overcoat;

an encapsulating material, said encapsulating material encapsulating both said first circuit portion, said protective overcoat, and said low-resistance structure.

8. The integrated circuit structure of

claim 7

, wherein said low resistance material is copper.

9. The integrated circuit structure of

claim 7

, wherein said low resistance material is more than three times as thick as any other conductive layer.

10. An integrated circuit structure, comprising:

a first circuit portion enclosed by a protective overcoat with bond pad openings, said first circuit portion including a metallization layer which forms a first electrode of a capacitor;

a low-resistance structure which forms a second electrode of a capacitor, said low-resistance structure being at least partially outside said protective overcoat;

an encapsulating material, said encapsulating material encapsulating both said first circuit portion, said protective overcoat, and said low-resistance structure.

11. The integrated circuit structure of

claim 10

, wherein said low resistance material is copper.

12. The integrated circuit structure of

claim 10

, wherein said low resistance material is more than three times as thick as any other conductive layer.

13. An integrated circuit structure, comprising an inductor, a high-Q capacitor, and a power transistor on the same chip.

15. The method of

claim 13

, wherein said low resistance material is copper.

16. The method of

claim 13

, wherein said low resistance material is more than three times as thick as any other conductive layer.

18. The method of

claim 16

, wherein said low resistance material is copper.

19. The method of

claim 16

, wherein said low resistance material is more than three times as thick as any other conductive layer.

14. A fabrication method, comprising the steps of:

(a.) covering a first circuit portion with a protective overcoat;

(b.) forming bond pad openings through said protective overcoat; and

(c.) forming an inductor of a low-resistance material on an exposed surface of said protective overcoat.

17. A fabrication method, comprising the steps of:

(a.) forming a first circuit portion which includes a first electrode of a capacitor;

(b.) covering said first circuit portion with a protective overcoat;

(c.) forming openings through said protective overcoat including bond pad openings and an opening at said first electrode;

(d.) depositing a capacitor dielectric over exposed portions of said first electrode; and

(e.) forming a second electrode of said capacitor overlying said first electrode, said second electrode at least partially overlying said protective overcoat.

20. A method of fabrication, comprising the step of forming an inductor, a high-Q capacitor, and a power transistor on a single semiconductor chip.