Delay circuit

• US 20010020861A1
• Filed: 03/06/2001
• Published: 09/13/2001
• Est. Priority Date: 03/08/2000
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Hirose, Yukitoshi
• Granted Patent: US 6,448,833 B2
• Time in Patent Office: Days
• US Class Current: 327/284
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A delay circuit using MOS transistors for use of load capacitance which produces a stable delay effect for variations in signal voltage is provided. A gate of a P-type MOS transistor for load capacitance and a gate of an N-type MOS transistor for load capacitance are connected to a signal line. A resistor and CMOS inverters are used to apply a boosted voltage higher than a supply voltage VDD to a source-drain of the P-type MOS transistor for load capacitance and a substrate voltage lower than a ground voltage to a source-drain of the N-type MOS transistor for load capacitance. As a result, a gate voltage range for allowing the MOS transistors for load capacitance to have a capacitance is extended, and a stable delay effect is assured for a widened variation of signal current flowing on the signal line.

Claims

1. A delay circuit comprising:

a P-type MOS transistor for load capacitance whose gate electrode is connected to a signal line and source and drain electrodes are connected to each other;

an N-type MOS transistor for load capacitance whose gate electrode is connected to said signal line and source and drain electrodes are connected to each other;

first power supply means for applying a boosted voltage higher than a supply voltage VDD to the connection of source and drain of said P-type MOS transistor for load capacitance; and

second power supply means for applying a substrate voltage lower than a ground voltage to the connection of source and drain of said N-type MOS transistor for load capacitance.

2. The delay circuit according to

claim 1

, further comprising:

means for switching between said boosted voltage higher than said supply voltage VDD and a voltage equal to or lower than said ground voltage as a voltage applied by said first power supply means to said connection of source and drain of said P-type MOS transistor for load capacitance; and

means for switching between a voltage equal to or higher than said supply voltage VDD and said substrate voltage lower than said ground voltage as a voltage applied by said second power supply means to said connection of source and drain of said N-type MOS transistor for load capacitance.

3. A delay circuit comprising:

a P-type MOS transistor for load capacitance whose gate is connected to a signal line and source and drain are connected to each other;

an N-type MOS transistor for load capacitance whose gate is connected to said signal line and source and drain are connected to each other;

a first CMOS inverter whose output terminal is connected to the connection of source and drain of said P-type MOS transistor for load capacitance;

first power supply means for applying a voltage higher than a supply voltage VDD to a higher potential side of said first CMOS inverter and for applying a voltage equal to or lower than a ground voltage to a lower potential side of said first CMOS inverter;

a second CMOS inverter whose output terminal connected to the connection of source and drain of said N-type MOS transistor for load capacitance;

second power supply means for applying a voltage equal to or higher than said supply voltage to a higher potential side of said second CMOS inverter and for applying a substrate voltage lower than said ground voltage to a lower potential side of said second CMOS inverter; and

switching means for applying a voltage for controlling the operations of said first and second CMOS inverters to said first and second CMOS inverters to switch between the voltage on the higher potential side and the voltage on the lower potential side as outputs from said first and second CMOS inverters.

4. The delay circuit according to

claim 3

, wherein said switching means includes an inverter having an output terminal connected to an input terminal of one of said first and second CMOS inverters and applies a potential with a phase reversed of the other CMOS inverter.

5. The delay circuit according to

claim 3

, wherein said switching means comprise said inverter and a plurality of fuses.

6. The delay circuit according to

claim 4

, wherein said switching means comprises said inverter and a plurality of fuses.

7. The delay circuit according to

claim 3

, wherein said switching means employs said inverter and a resistor.

8. The delay circuit according to

claim 4

, wherein said switching means employs said inverter and a resistor.