×

Delay circuit

  • US 20010020861A1
  • Filed: 03/06/2001
  • Published: 09/13/2001
  • Est. Priority Date: 03/08/2000
  • Status: Active Grant
First Claim
Patent Images

1. A delay circuit comprising:

  • a P-type MOS transistor for load capacitance whose gate electrode is connected to a signal line and source and drain electrodes are connected to each other;

    an N-type MOS transistor for load capacitance whose gate electrode is connected to said signal line and source and drain electrodes are connected to each other;

    first power supply means for applying a boosted voltage higher than a supply voltage VDD to the connection of source and drain of said P-type MOS transistor for load capacitance; and

    second power supply means for applying a substrate voltage lower than a ground voltage to the connection of source and drain of said N-type MOS transistor for load capacitance.

View all claims
  • 8 Assignments
Timeline View
Assignment View
    ×
    ×