IC tag and method for production thereof

• US 20010020896A1
• Filed: 03/02/2001
• Published: 09/13/2001
• Est. Priority Date: 03/10/2000
• Status: Abandoned Application

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Higuchi, Tutomu
• Application Number:
  US09/798,282
• Publication Number:
  US 20010020896A1
• Time in Patent Office: Days
• US Class Current: 340/572.7
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07779 the inductive antenna being a coil
• CPC Class Codes: G06K 19/07783 the coil being planar

Abstract

An IC tag includes a plane coil which is made by a conductor wire coated with an insulator wound several times in a plane, the plane coil having terminal portions and defining a central vacant area encircled by the wound wires. A semiconductor element is arranged in the central vacant area and placed in the plane and having a thickness substantially same as or smaller than a thickness of the plane coil, the semiconductor element having electrodes which are electrically connected to the terminal portions of the plane coil.

Claims

1. An IC tag comprising:

a plane coil comprising a conductor wire coated with an electrically insulating layer, said wire being wound several times in a plane to form a spiral loop of wire, said plane coil having respective terminal portions and defining a central vacant area encircled by said wound wire; and

a semiconductor element having a thickness substantially the same as the thickness of said plane coil and arranged in said central vacant area in said plane, said semiconductor element having electrodes which are electrically connected to said respective terminal portions of the plane coil.

2. An IC tag as set forth in

claim 1

, wherein said semiconductor element is accommodated in a protective frame which has a thickness substantially the same as the thickness of said semiconductor element and is flatly arranged in said central vacant area of the plane coil.

3. An IC tag as set forth in

claim 1

, wherein said semiconductor element is supported on, and adhered to, the one of the surfaces of an adhesive film to which said plane coil is also adhered.

4. An IC tag as set forth in

claim 3

, wherein said adhesive film has first and second adhesive layers on the respective surfaces thereof, and said plane coil and said semiconductor element are adhered to said first adhesive layer, while said second adhesive layer is covered with a removable film.

5. An IC tag as set forth in

claim 1

, wherein said semiconductor element is held in position by means of a resin filled in a gap between an outer circumference of said semiconductor element and an inner periphery of said plane coil.

6. An IC tag as set forth in

claim 1

, wherein said semiconductor element is supported in position only by a tightening force of said plane coil.

7. An IC tag as set forth in

claim 1

, wherein said wire of the plane coil is wound in such a manner that adjacent loops of wire are in contact with each other.

8. An IC tag as set forth in

claim 1

, wherein said wire of the plane coil is further coated with a hot-melting or fusing layer so as to cover said electrically insulating layer of the wire, so that the adjacent loops of wire are tightly connected to each other by means of said hot-melted or fused layer.

9. An IC tag as set forth in

claim 1

, wherein adjacent loops of wire are tightly connected to each other by means of a resin which is filled in a gap between outer surfaces of said loops of wire.

10. An IC tag as set forth in

claim 1

, wherein said electrodes of the semiconductor element are electrically connected to said terminal portions of the plane coil by means of a connecting pattern formed of an electrically conductive paste.

11. A method of producing an IC tag comprising the following steps of:

winding a conductor wire coated with an insulator several times in a plane so as to form a plane coil to define a spiral loop of wire and a central vacant area encircled by said wound wire in which a semiconductor element can be arranged;

adhering a support film to one of surfaces of said plane coil so as to cover at least said central vacant area;

arranging said semiconductor element in said central vacant area of the plane coil so that said semiconductor element is supported by said support film; and

electrically connecting said semiconductor element to said plane coil.

12. A method as set forth in

claim 11

, wherein said wire is wound in such a manner that adjacent loops of wire are in contact with each other.

13. A method as set forth in

claim 11

, wherein said support film is an adhesive film having first and second adhesive layers on respective surfaces thereof, wherein said semiconductor element and said plane coil are adhered to said first adhesive surface, while said second adhesive layer is covered with a removable film.

14. A method of producing an IC tag comprising the following steps of:

clamping a semiconductor element in a thickness direction thereof between a pair of flat clamping jigs;

forming a plane coil by winding a conductor wire coated with an insulator several times within a gap defined between said pair of clamping jigs around an outer circumference of said semiconductor element while it is being clamped by said jigs so that adjacent loops of wire are in contact with each other; and

electrically connecting said semiconductor element to said plane coil.

15. A method as set forth in

claim 14

, wherein said wire of the plane coil is further coated with a hot-melting or fusing layer so as to cover said electrically insulating layer of the wire, so that said plane coil is formed by heating said hot-melting or fusing layer to tightly connect said adjacent loops of wire.

16. A method of producing an IC tag comprising the following steps of:

clamping a semiconductor element and a protective frame in a thickness direction thereof between a pair of flat clamping jigs in such a manner that said semiconductor element is encircled by said protective frame;

forming a plane coil by winding a conductor wire coated with an insulator several times within a gap defined between said pair of clamping jigs around an outer circumference of said protective frame while said frame is being clamped by said jigs so that adjacent loops of wire are in contact with each other; and

electrically connecting said semiconductor element to said plane coil.

17. A method as set forth in

claim 16

, wherein said wire of the plane coil is further coated with a hot-melting or fusing layer so as to cover said electrically insulating layer of the wire, so that said plane coil is formed by heating said hot-melting or fusing layer to tightly connect said adjacent loops of wire.