Vector SIMD processor

• US 20010021941A1
• Filed: 03/08/2001
• Published: 09/13/2001
• Est. Priority Date: 03/13/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamada, Tetsuya, Arakawa, Fumio
• Granted Patent: US 7,028,066 B2
• Time in Patent Office: Days
• US Class Current: 708/514
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with SIMD and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining the efficiency of the floating-point length-4 vector inner product execution units is to be implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.

Claims

1. A data processor having an SIMD type execution unit:

said data processor having an instruction to cause said SIMD type execution unit to process vector data.

2. A data processor, as claimed in

claim 1

, wherein:

said SIMD type execution unit has a plurality of execution units for performing multiply-add operations on floating-point numbers.

3. A data processor for executing instructions in an instruction set and having an SIMD type execution unit, wherein:

said instruction set includes an instruction for causing said SIMD type execution unit to operate on vector data.

4. A data processor, as claimed in

claim 3

, wherein:

said SIMD type execution unit has a plurality of execution units for performing multiply-add operations on floating-point numbers.

5. A data processor for executing instructions in an instruction set, wherein:

said instruction set includes an instruction for causing said data processor to calculate the sum of the inner product of vectors and scalar data.

6. A data processor, as claimed in

claim 5

:

said data processor having a floating-point execution unit for calculating the inner product of a length-4 vector and another length-4 vector and the sum of said product and scalar data.

7. A data processor, as claimed in

claim 6

, wherein:

said floating-point execution unit has a 9 input adder.

8. A data processor for executing instructions in an instruction set, wherein:

said instruction set includes an instruction for causing said data processor to calculate the product of matrix data and vector data.

9. A data processor, as claimed in

claim 8

:

said data processor having a plurality of floating-point execution units for calculating the inner product of a vector and another vector.

10. A data processor, as claimed in

claim 8

, wherein:

said matrix data are 4×

4 matrix data and said vector data are length-4 vectors.

11. A data processor, as claimed in

claim 9

, wherein:

each of said plurality of floating-point execution units is an execution unit capable of calculating the sum of said inner product and scalar data.

12. A data processing system, as claimed in

claim 11

, wherein:

said execution unit has a 9 input adder.