Network interface device employing a DMA command queue

• US 20010021949A1
• Filed: 05/14/2001
• Published: 09/13/2001
• Est. Priority Date: 10/14/1997
• Status: Active Grant

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Philbrick, Clive M., Starr, Daryl D., Blightman, Stephen E.J.
• Granted Patent: US 7,133,940 B2
• Time in Patent Office: Days
• US Class Current: 709/219
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 67/62 Establishing a time schedule for servicing the requests
• CPC Class Codes: H04L 67/63 Routing a service request depending on the request content or context
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A network interface device couples a host computer to a network. The network interface device includes a processor and a DMA controller. The processor causes the DMA controller to perform multiple DMA commands before the processor takes a particular software branch. The processor issues the DMA commands by placing the DMA commands in a memory and then pushing values indicative of the DMA commands onto a DMA command queue. The values are popped off the DMA command queue and are executed by the DMA controller one at a time. The DMA commands are executed in the same order that they were issued by the processor. The processor need not monitor multiple DMA commands to make sure they have all been completed before the software branch is taken, but rather the processor pops a DMA command complete queue to make sure that the last of the DMA commands has been completed.

Claims

1. A method, comprising:

(a) maintaining on a network interface device a DMA command queue;

(b) a processor on the network interface device causing a value to be pushed onto the DMA command queue, the value being indicative of corresponding DMA command;

(c) popping a value off the DMA command queue, a DMA controller on the network interface device then executing a DMA command indicated by the popped value;

(d) repeating (b) and (c) such that a first portion of data is transferred from host storage to a local memory on the network interface device and such that a second portion of data is transferred from the host storage to the local memory on the network interface device; and

(e) after both the first portion and the second portion are present in the local memory, outputting the first and second portions of data from the network interface device to a network, the first and second portions making up at least a part of a data payload of a network communication.

2. The method of

claim 1

, further comprising:

(f) maintaining a DMA command complete queue on the network interface device, the DMA controller pushing values onto the DMA command complete queue, the processor popping values off the DMA command conmplete queue.

3. The method of

claim 2

, wherein the processor uses the DMA command complete queue to determine that the first and the second portions of data are both present in local memory on the network interface device.

4. The method of

claim 1

, wherein the network interface device comprises queue manager hardware, the queue manager hardware maintaining the DMA command queue in static random access memory (SRAM), wherein the processor, the queue manager hardware, the SRAM, and the DMA controller are all part of the same integrated circuit.

5. The method of

claim 1

, wherein the pushing of (b) occurs twice before the popping of (c) occurs once.

6. The method of

claim 1

, wherein each of the values on the DMA command queue is a DMA command.

7. The method of

claim 1

, wherein each of the values on the DMA command queue comprises a pointer to a DMA command.

8. The method of

claim 1

, wherein each of the values on the DMA command queue is a number that identifies a location where a DMA command is stored.

9. The method of

claim 1

, wherein the network interface device is an expansion card coupled to a host computer, the host storage being part of the host computer.

10. The method of

claim 1

, wherein the network interface device is a part of a host computer.

11. A network interface device, comprising:

queue manager hardware that maintains a DMA command queue;

a processor coupled to the queue manager hardware, the processor causing values to be pushed onto the DMA command queue;

a DMA controller coupled to the queue manager hardware, the DMA controller executing DMA commands, the DMA commands executed being indicated by values popped off the DMA command queue;

local memory that temporarily stores a first portion of data transferred by execution of one or more DMA commands from data storage on a host coupled to the network interface device into the local memory, the local memory also temporarily storing a second portion of data transferred by execution of one or more DMA commands from the data storage on the host to the local memory; and

physical layer interface and media access control circuitry, the physical layer interface and media access control circuitry outputting the first and second portions of data from the network interface device to a network, the first and second portions of data being output in the form of a data payload of a network communication.

12. The network interface device of

claim 11

, wherein the local memory is dynamic random access memory (DRAM).

13. The network interface device of

claim 12

, wherein the queue manager hardware stores at least part of the DMA command queue in static random access memory (SRAM).

14. A method, comprising:

(a) maintaining on a network interface device a DMA command queue, the DMA command queue being maintained by queue manager hardware on the network interface device;

(b) a processor on the network interface device causing a value to be pushed onto the DMA command queue, the value being indicative of corresponding DMA command;

(c) popping a value off the DMA command queue, a DMA controller on the network interface device then executing a DMA command indicated by the popped value;

(d) repeating (b) and (c) such that a first portion of data is transferred from a first place on the network interface device to a second place on the network interface device, and such that a second portion of data is transferred from the first place on the network interface device to the second place on the network interface device; and

(e) after both the first portion and the second portion have been transferred to the second place in (d), the processor taking a software branch; and

(f) after taking the software branch, the processor outputting the first and second portions of data from the network interface device.

15. The method of

claim 14

, wherein the processor outputs the first and second portions of data in (f) to a network.

16. The method of

claim 14

, wherein the processor outputs the first and second portions of data in (f) to a host computer.

17. The method of

claim 14

, wherein the first place is a dynamic random access memory (DRAM) and wherein the second place is a bus interface.

18. The method of

claim 14

, wherein the first place is a bus interface and wherein the second place is a dynamic random access memory (DRAM).

19. The method of

claim 14

, wherein the first place is a bus interface and wherein the second place is a static random access memory (SRAM).

20. The method of

claim 14

, wherein the first place is a static random access memory (SRAM) and wherein the second place is a bus interface.

21. A method, comprising:

(a) using a DMA command queue to ensure that a plurality of DMA moves are completed in a particular sequence, each of the DMA moves being a move of information from one location on a network interface device to another location on the network interface device, the DMA command queue being maintained by queue manager hardware on the network interface device, the DMA moves being carried out by a DMA controller, the DMA controller being a part of the network interface device; and

(b) outputting at least part of the information from the network interface device.

22. The method of

claim 23

, wherein the information output in (b) is output from the network interface device to a host computer, the host computer being coupled to the network interace device.

23. The method of

claim 21

, wherein the information output in (b) is output from the network interface device to a network.

24. The method of

claim 21

, wherein a first of the plurality of DMA moves is a move of at least a part of a frame of a session layer message, and wherein a second of the plurality of DMA moves is a move of at least a part of a subsequent frame of the session layer message.

25. The method of

claim 24

, wherein a processor pushes values onto the DMA command queue, each of the values being indicative of a different DMA command, and wherein the processor analyzes at least a part of the information moved in the first move, the processor doing the analyzing after the first move is complete.

26. The method of

claim 25

, wherein said one location on the network interface device is a dynamic random access memory (DRAM) and wherein said another location on the network interface device is a static random access memory (SRAM), wherein the first move is a move of information from a first buffer in the DRAM to a first buffer in the SRAM, and wherein the second move is a move of information from a second buffer in the DRAM to a second buffer in the SRAM.

27. The method of

claim 25

, wherein the processor does the analyzing before the second move is complete.

28. An apparatus, comprising:

means for maintaining a DMA command queue on a network interface device and for causing values to be pushed onto the DMA command queue, each of the values pushed onto the DMA command queue being indicative of a DMA command; and

a DMA controller that executes the plurality of DMA commands such that the DMA commands are completed in a particular order.

29. The apparatus of

claim 28

, wherein the means comprises a processor.

30. The apparatus of

claim 29

, wherein the means further comprises a hardware queue manager.