Electronic device and method of driving electronic device
First Claim
1. A method of driving an electronic device having n-bit grey scale comprising a step of:
- controlling a length of a turn on period of each of self light emitting elements, wherein;
one frame period is divided into n subframe periods SF1, SF2, . . . SFn;
said n subframe periods have address periods Ta1, Ta2, . . . , Tan and sustain periods Ts1, Ts2, . . . , Tsn, respectively;
the length of said sustain periods Ts1;
;
Ts2;
;
. . . ;
;
Tsn=2(n−
1);
;
2(n−
2);
;
20; and
at least one of said n subframe periods has such a period that one of said address periods and one of said sustain periods overlap.
1 Assignment
0 Petitions
Accused Products
Abstract
Problems such as insufficient brightness, caused by a reduction in duty ratio (the ratio of a light emitting period and a non-light emitting period), are improved upon in accordance with using a novel method of driving and a novel circuit in an electronic device. Signals are written into pixels of a plurality of differing lines during one gate signal line selection period. By arbitrarily setting, to a certain extent, the time from when a signal is input into the pixels of a certain line until the next signal is input to the same pixels, while ensuring the time for writing into the pixels, a sustain (turn on) period can be arbitrarily set and a high duty ratio is realized.
209 Citations
18 Claims
-
1. A method of driving an electronic device having n-bit grey scale comprising a step of:
-
controlling a length of a turn on period of each of self light emitting elements, wherein;
one frame period is divided into n subframe periods SF1, SF2, . . . SFn;
said n subframe periods have address periods Ta1, Ta2, . . . , Tan and sustain periods Ts1, Ts2, . . . , Tsn, respectively;
the length of said sustain periods Ts1;
;
Ts2;
;
. . . ;
;
Tsn=2(n−
1);
;
2(n−
2);
;
20; and
at least one of said n subframe periods has such a period that one of said address periods and one of said sustain periods overlap. - View Dependent Claims (10)
-
-
2. A method of driving an electronic device having n-bit grey scale comprising a step of:
-
controlling a length of a turn on period of each of self light emitting elements, wherein;
one frame period is divided into n subframe periods SF1, SF2, . . . , SFn;
said n subframe periods have address periods Ta1, Ta2, . . . , Tan and sustain periods Ts1, Ts2, . . . , Tsn,respectively;
the length of said sustain periods Ts1;
;
Ts2;
;
. . . ;
;
Tsn=2(n−
1);
;
2(n−
2);
;
. . . ;
;
20;
a plurality of gate signal line selection periods within each of said n subframe periods, each of said plurality of gate signal lines has m sub-gate signal line selection periods;
at most one of said plurality of gate signal line is selected within each of said m sub-gate signal line selection periods; and
at most (m×
n)-th times of vertical scanning are performed in said one frame period. - View Dependent Claims (11)
-
-
3. A method of driving an electronic device having n-bit grey scale comprising a step of:
-
controlling a length of a turn on period of each of self light emitting elements, wherein;
one frame period is divided into n subframe periods SF1, SF2, . . . , SFn;
said n subframe periods have address periods Ta1, Ta2, . . . , Tan and sustain periods Ts1, Ts2, . . . , Tsn,respectively;
the length of said sustain periods Ts1;
;
Ts2;
;
. . . ;
;
Tsn=2(n−
1);
;
2(n−
2);
;
. . . ;
;
20;
a plurality of gate signal line selection periods within each of said n subframe periods, each of said plurality of gate signal lines has m sub-gate signal line selection periods;
at most one of said plurality of gate signal line is selected within each of said m sub-gate signal line selection periods; and
at most m gate signal lines, are different from one another, are selected within each of said plurality of gate signal line selection periods. - View Dependent Claims (12)
-
-
4. A method of driving an electronic device having n-bit grey scale comprising a step of:
-
controlling a length of a turn on period of each of self light emitting elements, wherein;
one frame period is divided into n subframe periods SF1, SF2, . . . , SFn;
said n subframe periods have address periods Ta1, Ta2, . . . , Tan and sustain periods Ts1, Ts2, . . . , Tsn, respectively;
the length of said sustain periods Ts1;
;
Ts2;
;
. . . ;
;
Tsn=2(n−
1);
;
2(n−
2);
;
. . . ;
;
20;
a plurality of gate signal line selection periods within each of said n subframe periods, each of said plurality of gate signal lines has m sub-gate signal line selection periods;
at most one of said plurality of gate signal line is selected within each of said m sub-gate signal line selection periods;
at most m gate signal lines, are different from one another, are selected within each of said plurality of gate signal line selection periods;
reset signal is inputted within such a period that an address period within one of said n subframe periods and an address period within another one of said n subframe periods overlap; and
said self light emitting elements are in turn off state within such a period that said reset signal is inputted. - View Dependent Claims (13)
-
-
5. An electronic device comprising:
- a source signal line driver circuit;
a gate signal line driver circuit; and
a pixel portion having a plurality of self light emitting elements arranged in a matrix shape;
wherein;
n-bit grey scale control for controlling the length of a turn on period of the self light emitting elements is performed;
one frame period has n subframe periods SF1, SF2, . . . , SFn;
the n subframe periods SF1, SF2, . . . , SFn, have;
address (write in) periods Ta1, Ta2, . . . , Tan, respectively; and
sustain (turn on) periods Ts1, Ts2, . . . , Tsn, respectively;
the length of the sustain (turn on) periods Ts1;
;
Ts2;
;
. . . ;
;
Tsn=2(n−
1);
;
2(n−
2);
;
. . . ;
;
20; and
at least one of said n subframe periods has such a period that one of said address periods and one of said sustain periods overlap. - View Dependent Claims (14)
- a source signal line driver circuit;
-
6. An electronic device comprising:
- a source signal line driver circuit;
a gate signal line driver circuit; and
a pixel portion having a plurality of self light emitting elements arranged in a matrix shape;
wherein;
n-bit grey scale control for controlling the length of a turn on period of the self light emitting elements is performed;
one frame period has n subframe periods SF1, SF2, . . . , SFn;
the n subframe periods SF1, SF2, . . . , SFn have;
address (write in) periods Ta1, Ta2, . . . , Tan, respectively; and
sustain (turn on) periods Ts1, Ts2, . . . , Tsn, respectively;
the length of the sustain (turn on) periods Ts1;
;
Ts2;
;
. . . ;
;
Tsn=2(n−
1);
;
2(n−
2);
;
. . . ;
;
20; and
a plurality of gate signal line selection periods within each of said n subframe periods, each of said plurality of gate signal lines has m sub-gate signal line selection periods;
at most one of said plurality of gate signal line is selected within each of said m sub-gate signal line selection periods; and
at most (m×
n)-th times of vertical scanning are performed in said one frame period. - View Dependent Claims (15)
- a source signal line driver circuit;
-
7. An electronic device comprising:
- a source signal line driver circuit;
a gate signal line driver circuit; and
a pixel portion having a plurality of self light emitting elements arranged in a matrix shape;
wherein;
one frame period has n subframe periods SF1, SF2, . . . , SFn;
the n subframe periods SF1, SF2, . . . , SFn have;
address (write in) periods Ta1, Ta2, . . . , Tan, respectively; and
sustain (turn on) periods Ts1, Ts2, . . . , Tsn, respectively;
the length of the sustain (turn on) periods Ts1;
;
Ts2;
;
. . . ;
;
Tsn=2(n−
1);
;
2(n−
2);
;
. . . ;
;
20;
a plurality of gate signal line selection periods within each of said n subframe periods, each of said plurality of gate signal lines has m sub-gate signal line selection periods;
at most one of said plurality of gate signal line is selected within each of said m sub-gate signal line selection periods; and
at most m gate signal lines, are different from one another, are selected within each of said plurality of gate signal line selection periods. - View Dependent Claims (16)
- a source signal line driver circuit;
-
8. An electronic device comprising:
- a source signal line driver circuit;
a gate signal line driver circuit; and
a pixel portion having a plurality of self light emitting elements arranged in a matrix shape;
wherein;
one frame period has n subframe periods SF1, SF2, . . . , SFn;
the n subframe periods SF1, SF2, . . . , SFn have;
address (write in) periods Ta1, Ta2, . . . , Tan, respectively; and
sustain (turn on) periods Ts1, Ts2, . . . , Tsn, respectively;
the length of the sustain (turn on) periods Ts1;
;
Ts2;
;
. . . ;
;
Tsn=2(n−
1);
;
2(n−
2);
;
. . . ;
;
20; and
a plurality of gate signal line selection periods within each of said n subframe periods, each of said plurality of gate signal lines has m sub-gate signal line selection periods;
at most one of said plurality of gate signal line is selected within each of said m sub-gate signal line selection periods;
at most m gate signal lines, are different from one another, are selected within each of said plurality of gate signal line selection periods;
reset signal is inputted within such a period that an address period within one of said n subframe periods and an address period within another one of said n subframe periods overlap; and
said self light emitting elements are in turn off state within such a period that said reset signal is inputted. - View Dependent Claims (17)
- a source signal line driver circuit;
-
9. An electronic device comprising:
- a source signal line driver circuit;
a gate signal line driver circuit; and
a pixel portion in which a plurality of self light emitting elements are arranged in an matrix shape having a rows and b columns;
wherein;
the source signal driver circuit uses a plurality of source driver circuits having;
at least one first shift register circuit;
a first memory circuit for storing a digital image signal; and
a second memory circuit for storing an output signal of the first memory circuit;
the gate signal line driver circuit uses a plurality of gate driver circuits having;
at least one second shift register circuit; and
at least one buffer circuit;
one frame period has n subframe periods SF1, SF2, . . . , SFn;
a plurality of gate signal line selection periods within the subframe periods has m sub-gate signal line selection periods;
write in to at most one gate signal line is performed in the sub-gate signal line selection periods;
write in of signals to at most m gate signal lines is completed within one gate signal line selection period;
one source signal line is electrically connected to a maximum of m source driver circuits, through a first switching circuit;
one gate signal line is electrically connected to a maximum of m gate driver circuits, through a second switching circuit;
the source signal line driver circuit has a maximum of b×
m source driver circuits;
the gate signal line driver circuit has a maximum of a×
m gate driver circuits;
the first switching circuit selects only one electrically connected source driver circuit, from among the m source driver circuits, during one dot data write in period, connects to the source signal line, and performs signal write in; and
the second switching circuit selects only one electrically connected gate driver circuit, from among the m gate driver circuits, during one sub-gate signal line selection period, connects to the gate signal line, and performs write in. - View Dependent Claims (18)
- a source signal line driver circuit;
Specification