Exponent unit of data processing system
First Claim
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1. An exponent unit adapted to receive an operand and to output an exponent of the operand, comprising:
- a detection device adapted to detect a number of consecutive bits of the operand having a same value as a most significant bit (MSB) of the operand, and to output a detection value corresponding thereto;
a mantissa and carry control device adapted to output the detection value as a mantissa signal in at least one of a single precision mode and, when a previous first status bit is set and the MSB is identical to a previous second status bit, in a double precision mode, and to generate a carry signal in the double precision mode, when the previous first status bit is set and the MSB is identical to the previous second status bit;
an augend control device adapted to output an exponent of a previous operand as an augend signal;
a logic circuit adapted to set a first status bit and to set a second status bit to a lowest bit of the operand, when all bits of the operand have an identical value; and
an adder adapted to add the mantissa signal, the augend signal, and the carry signal to obtain a sum thereof, and to output the sum as the exponent of the operand, wherein the single precision mode and the double precision mode are sequentially generated, and the exponent of the operand is equal to the number of consecutive bits of the operand having the same value as the MSB of the operand.
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Abstract
An exponent unit receives an operand and outputs an exponent of the operand that is equal to the number of consecutive bits of the operand that have the same value as the most significant bit (MSB) of the operand. The exponent unit can obtain an exponent value of an operand having a bit width that is greater than a processing bit width of a leading one detector (or a leading zero detector).
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Citations
20 Claims
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1. An exponent unit adapted to receive an operand and to output an exponent of the operand, comprising:
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a detection device adapted to detect a number of consecutive bits of the operand having a same value as a most significant bit (MSB) of the operand, and to output a detection value corresponding thereto;
a mantissa and carry control device adapted to output the detection value as a mantissa signal in at least one of a single precision mode and, when a previous first status bit is set and the MSB is identical to a previous second status bit, in a double precision mode, and to generate a carry signal in the double precision mode, when the previous first status bit is set and the MSB is identical to the previous second status bit;
an augend control device adapted to output an exponent of a previous operand as an augend signal;
a logic circuit adapted to set a first status bit and to set a second status bit to a lowest bit of the operand, when all bits of the operand have an identical value; and
an adder adapted to add the mantissa signal, the augend signal, and the carry signal to obtain a sum thereof, and to output the sum as the exponent of the operand, wherein the single precision mode and the double precision mode are sequentially generated, and the exponent of the operand is equal to the number of consecutive bits of the operand having the same value as the MSB of the operand. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data processing system comprising:
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an exponent unit adapted to output an exponent of an operand that is equal to a number of consecutive bits of the operand having a same value as a most significant bit (MSB) of the operand;
a status register adapted to store previous first and second status bits; and
a decoder adapted to decode an instruction comprising the operand, to supply the operand and the previous first and second status bits stored in said status register to said exponent unit when the decoded instruction is an exponent instruction, and to output a mode signal having a first level or a second level depending upon whether the decoded instruction is a single precision exponent instruction or a double precision exponent instruction, respectively, wherein the exponent unit comprises;
first and second latches adapted to latch the previous first and second status bits supplied from said status register, respectively;
a detection device adapted to detect the number of consecutive bits of the operand having the same value as the MSB, and to output a detection value corresponding thereto;
a mantissa and carry control device adapted to output the detection value as a mantissa signal when the mode signal is at the first level or when the mode signal is at the second level, the previous first status bit is set, and the previous second status bit is identical to the MSB, and to output a carry signal when the mode signal is at the second level, the previous first status bit is set, and the previous second status bit is identical to the MSB;
an augend control device adapted to output an exponent of a previous operand as an augend signal when the mode signal is at the second level;
a logic circuit adapted to set a first status bit and to set a second status bit to a lowest bit of the operand, when all bits of the operand have an identical value; and
an adder adapted to add the mantissa signal, the augend signal, and the carry signal to obtain a sum thereof, and to output the sum as the exponent of the operand;
wherein said first and second latches are further adapted to retain a latched value for a predetermined time, and the single precision exponent instruction and the double precision exponent instruction are sequentially generated. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. An exponent unit adapted to receive an operand and to output an exponent of the operand, comprising:
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a detection and control device adapted to detect a number of consecutive bits of the operand having a same value as a most significant bit (MSB) of the operand, to output a mantissa signal corresponding thereto in at least one of a single precision mode and, when a previous first status bit is set and the MSB is identical to a previous second status bit, in a double precision mode, and to generate a carry signal in the double precision mode, when the previous first status bit is set and the MSB is identical to the previous second status bit;
an augend control device adapted to output an exponent of a previous operand as an augend signal; and
an adder adapted to add the mantissa signal, the augend signal, and the carry signal to obtain a sum thereof, and to output the sum as the exponent of the operand, wherein the single precision mode and the double precision mode are sequentially generated, and the exponent of the operand is equal to the number of consecutive bits of the operand having the same value as the MSB of the operand. - View Dependent Claims (20)
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Specification