Trench DMOS transistor having a double gate structure

• US 20010023961A1
• Filed: 06/01/2001
• Published: 09/27/2001
• Est. Priority Date: 03/17/2000
• Status: Active Grant

• Current Assignee: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
• Original Assignee: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man
• Granted Patent: US 6,518,127 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench DMOS transistor cell is provided, which is formed on a substrate of a first conductivity type. A body region, which has a second conductivity type, is located on the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. The insulating layer includes first and second portions that contact one another at an interface. The first portion of the insulating layer has a layer thickness greater than the second portion. The interface is located at a depth above a lower boundary of the body region. A conductive electrode is formed in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench.

Claims

1. A trench DMOS transistor cell, comprising:

a substrate of a first conductivity type;

a body region on the substrate, said body region having a second conductivity type;

at least one trench extending through the body region and the substrate;

an insulating layer that lines the trench, said insulating layer including first and second portions that contact one another at an interface, said first portion having a layer thickness greater than said second portion, said interface being located at a depth above a lower boundary of the body region;

a conductive electrode in the trench overlying the insulating layer; and

a source region of the first conductivity type in the body region adjacent to the trench.

2. The DMOS transistor cell of

claim 1

further comprising a drain electrode disposed on a surface of the substrate opposing the body region.

3. The DMOS transistor cell of

claim 1

wherein said insulating layer is an oxide layer.

4. The DMOS transistor cell of

claim 1

wherein said conductive electrode includes polysilicon.

5. The DMOS transistor cell of

claim 1

wherein said interface is located at a depth between an upper and lower boundary of the body region.

6. The DMOS transistor cell of

claim 1

wherein said conductive electrode includes a layer of polysilicon and silicide.

7. A trench DMOS transistor structure that includes a plurality of individual trench DMOS transistor cells formed on a substrate of a first conductivity type, each of said individual trench DMOS transistor cells comprising:

a body region on the substrate, said body region having a second onductivity type;

at least one trench extending through the body region and the substrate;

an insulating layer that lines the trench, said insulating layer including first and second portions that contact one another at an interface, said first portion having a layer thickness greater than said second portion, said interface being located at a depth above a lower boundary of the body region;

a conductive electrode in the trench overlying the insulating layer; and

a source region of the first conductivity type in the body region adjacent to the trench.

8. The DMOS transistor structure of

claim 7

further comprising a drain electrode disposed on a surface of the substrate opposing the body region.

9. The DMOS transistor structure of

claim 7

wherein said insulating layer is an oxide layer.

10. The DMOS transistor structure of

claim 7

wherein said conductive electrode includes polysilicon.

11. The DMOS transistor structure of

claim 7

wherein said interface is located at a depth between an upper and lower boundary of the body region.

12. The DMOS transistor structure of

claim 7

wherein said conductive electrode includes a layer of polysilicon and silicide.

13. The DMOS transistor structure of

claim 7

wherein at least one of said trench DMOS transistor cells have a closed cell geometry.

14. The DMOS transistor structure of

claim 7

wherein at least one of said trench DMOS transistor cells have an open cell geometry.

15. A method for forming a trench DMOS, comprising the steps of:

providing an article comprising a substrate of a first conductivity type and a body region of a second conductivity type, said article having a trench which extends through said body region and said substrate;

depositing an insulating layer in the trench, said insulating layer including first and second portions that contact one another at an interface, said first portion having a layer thickness greater than said second portion, said interface being located at a depth above a lower boundary of the body region;

forming a conductive electrode in the trench; and

forming a source region of the first conductivity type in the body region.

16. The method of

claim 15

wherein said insulating layer is deposited so that said interface is located at a depth between an upper and lower boundary of the body region.

17. The method of

claim 15

wherein the steps of depositing the insulating layer and forming the conductive electrode includes the steps of:

depositing a first insulating layer;

depositing a first conductive electrode layer;

etching a portion of said first insulating layer to define said first and second portions of the insulating layer; and

depositing a second conductive electrode layer over said first conductive electrode layer, said first and second conductive electrode layers forming said conductive electrode.