Semiconductor package using terminals formed on a conductive layer of a circuit board

• US 20010023982A1
• Filed: 05/24/2001
• Published: 09/27/2001
• Est. Priority Date: 06/11/1998
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Robert F. Wallace
• Inventors: Wallace, Robert F.
• Granted Patent: US 6,867,485 B2
• Time in Patent Office: Days
• US Class Current: 257/679
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/5388 for flat cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/117 Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 2201/09127 PCB or component having an integral separable or breakable part
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: H05K 2201/2018 : Presence of a frame in a printed circuit or printed circuit assembly
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence

Abstract

A small package is provided for a flash EEPROM memory. The small package uses terminals which are part of a bottom conductive layer of a circuit board. In this manner, the final package can be quite thin. The circuit board can be connected to the integrated circuits and passive devices and can be encapsulated in plastic or glued to a plastic cover. In this manner, a thin and relatively inexpensive package can be formed. Additionally, the circuit board can have testing connections which can be removed before forming the final package.

Claims

1. A package including:

a circuit board;

an set of circuit elements on the circuit board, the set of circuit elements including at least one integrated circuit and passive components; and

packaging material surrounding the set of circuit elements and part of the circuit board, wherein one side of the circuit board includes a set of terminals that are visible from the side of the package, the set of terminals being positioned away from the edge of the circuit board.

2. The package of

claim 1

, wherein the packaging material includes molded plastic.

3. The package of

claim 2

, wherein the packaging material includes a bordering frame.

4. The package of

claim 1

, wherein one side of the circuit board is exposed.

5. The package of

claim 4

, wherein the exposed side of the circuit board material includes the set of terminals connected to the remainder of the circuit board by vias.

6. The package of

claim 5

, wherein the circuit board material is attached to the packaging material by epoxy.

7. The package of

claim 1

, wherein the circuit elements includes at least two integrated circuits and passive devices.

8. The package of

claim 7

, wherein the thickness of the package is less than 12 mils.

9. The package of

claim 1

, wherein the package is a flash EEPROM package.

10. A package including:

a circuit board;

at least one integrated circuit on the circuit board; and

packaging material surrounding the set of circuit elements and part of the circuit board, wherein one side of the circuit board is exposed, the exposed side of the circuit board material including a set of terminals connected to the remainder of the circuit board by vias.

11. The package of

claim 10

, wherein the circuit board material is attached to the packaging material by epoxy.

12. The package of

claim 10

, wherein on the exposed side of the circuit board only the set of terminals is exposed.

13. The package of

claim 10

, wherein the circuit elements includes at least two integrated circuits and passive devices.

14. The package of

claim 10

, wherein the thickness of the package is less than 12 mils.

15. The package of

claim 10

, wherein the package is a flash EEPROM package.

16. A package including:

a circuit board;

an set of circuit elements on the circuit board, the set of circuit elements including at least one integrated circuit and passive components; and

a plastic material encasing the set of circuit elements and part of the circuit board, wherein one side of the circuit board includes a set of terminals that are accessible from the side of the package, the set of terminals being positioned away from the edge of the circuit board.

17. The package of

claim 16

, wherein one side of the circuit board is exposed.

18. The package of

claim 17

, wherein the exposed side of the circuit board material includes the set of terminals connected to the remainder of the circuit board by vias.

19. The package of

claim 16

, wherein the circuit board material is attached to the packaging material by epoxy.

20. The package of

claim 16

, wherein on the exposed side of the circuit board only the set of terminals is exposed.

21. The package of

claim 16

, wherein the thickness of the package is less than 12 mils.

22. The package of

claim 16

, wherein the package is a flash EEPROM package.

23. A method comprising:

attaching an set of circuit elements to a circuit board, the set of circuit elements including at least one integrated circuit and passive components; and

thereafter, packaging the circuit board in plastic such that one side of the circuit board includes a set of terminals that are accessible from the side of the package.

24. The method of

claim 23

, wherein the packaging step includes placing plastic into a mold containing the circuit board.

25. The method of

claim 24

, wherein the packaging step includes clamping over terminals.

26. The method of

claim 23

, wherein the packaging step includes putting plastic into a mold with multiple chambers, each chamber having a different circuit board.

27. The method of

claim 23

, wherein the packaging step includes putting the circuit board in a border frame.

28. The method of

claim 23

, wherein the circuit board elements include two integrated circuits and the method further comprises

a first encapsulating step for the two integrated circuits.

29. The method of

claim 23

, wherein the first encapsulating step is such that there is a connecting region of encapsulant material formed between the two integrated circuits, the connecting region of encapsulant material being narrower than the integrated circuits.

30. A method comprising:

providing a circuit board with at least two integrated circuits formed thereon; and

encapsulating the at least two integrated circuits in an encapsulant material, the encapsulating step being such that there is a connecting region of encapsulant material formed between two of the at least two integrated circuits, the connecting region of encapsulant material being narrower than the two of the at least two integrated circuits.

31. The method of

claim 31

, further comprising, after the encapsulating step, packaging the circuit board.

32. A method comprising:

attaching an set of circuit elements to a circuit board, the set of circuit elements including at least one integrated circuit and passive components, the circuit board having test connections and terminals, the test connections being connected to test the set of circuit elements;

testing the set of circuit elements using the test connections;

thereafter, removing the test connections portion of the circuit board; and

thereafter, packaging the circuit board.

33. The method of

claim 32

, wherein the terminals are positioned on a side of the circuit board.

34. The method of

claim 32

, wherein the package is such that the terminals are exposed.

35. The method of

claim 32

, wherein the testing includes a burn-in testing.

36. The method of

claim 32

, further comprising programming at least one integrated circuit using the test connections.