System and method for fabricating logic devices comprising carbon nanotube transistors
First Claim
1. A logic device, comprising:
- a plurality of interconnecting carbon nanotube devices, wherein said interconnecting carbon nanotube devices comprise a plurality of electrically connected carbon nanotubes on one or more levels of a substrate, and wherein said carbon nanotubes are formed within at least one nanosized catalyst retaining structure in said substrate.
1 Assignment
0 Petitions
Accused Products
Abstract
Carbon nanotube devices and methods for fabricating these devices, wherein in one embodiment, the fabrication process consists of the following process steps: (1) generation of a template, (2) catalyst deposition, and (3) nanotube synthesis within the template. In another embodiment, a carbon nanotube transistor comprises a carbon nanotube having two or more defects, wherein the defects divide the carbon nanotube into three regions having differing conductivities. The defects may be introduced by varying the diameter of a template in which the carbon nanotube is fabricated and thereby causing pentagon-heptagon pairs which form the defects.
453 Citations
64 Claims
-
1. A logic device, comprising:
a plurality of interconnecting carbon nanotube devices, wherein said interconnecting carbon nanotube devices comprise a plurality of electrically connected carbon nanotubes on one or more levels of a substrate, and wherein said carbon nanotubes are formed within at least one nanosized catalyst retaining structure in said substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
18. A method of fabricating a carbon nanotube device, comprising the steps of:
-
fabricating a template of nanosized catalyst retaining structures within a substrate;
depositing catalyst within said nanosized catalyst retaining structures; and
synthesizing carbon nanotubes that conform to said template of said nanosized catalyst retaining structures. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
-
-
47. A method for manufacturing an array of transistors, comprising:
-
growing aligned carbon nanotubes within a catalyst retaining template; and
introducing one or more discontinuities within a structure of said carbon nanotubes, wherein said discontinuities are conductivity discontinuities along a vertical axis of said carbon nanotubes, wherein if one discontinuity is introduced a diode is formed and if two discontinuities is introduced a transistor is formed. - View Dependent Claims (48, 49, 50, 51, 52)
-
-
53. A carbon nanotube transistor, comprising:
a carbon nanotube with at least two defects in said carbon nanotube, and wherein said defects divide said carbon nanotube into three regions with differing conductivities. - View Dependent Claims (54, 55, 56, 57, 58)
-
59. A logic device, comprising:
-
a substrate;
a layer of insulating material in which at least one catalyst retaining structure is formed;
at least one carbon nanotube formed within said catalyst retaining structure, wherein said at least one carbon nanotube has at least two defects in said carbon nanotube, and wherein said defects divide said carbon nanotube into at least three regions with differing conductivities. - View Dependent Claims (60, 61, 62, 63, 64)
-
Specification