Conformal thin films over textured capacitor electrodes

• US 20010024387A1
• Filed: 02/22/2001
• Published: 09/27/2001
• Est. Priority Date: 12/03/1999
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Raaijmakers, Ivo, Haukka, Suvi P., Granneman, Ernst H. A.
• Granted Patent: US 6,831,315 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: H01L 21/02159 the material containing zirconium, e.g. ZrSiOx
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: Y10T 428/265 1 mil or less

Abstract

Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design. Alternately pulsed chemistries are also provided for depositing top electrode materials with continuous coverage of capacitor dielectric, realizing the full capacitance benefits of the underlying textured morphology.

Claims

1. A method of forming a capacitor in an integrated circuit, comprising:

constructing a bottom electrode including a textured silicon layer; and

depositing a dielectric layer over the textured silicon layer wherein depositing comprises;

forming no more than about one monolayer of a first material over the textured silicon layer by exposure to a first reactant species; and

reacting a second reactant species with the first material to leave no more than about one monolayer of a second material.

2. The method of

claim 1

, wherein the textured silicon layer comprises a hemispherical grain morphology.

3. The method of

claim 1

, wherein forming no more than about one monolayer comprises supplying a first chemistry substantially excluding the second reactant species and reacting comprises supplying a second chemistry substantially excluding the first reactant species.

4. The method of

claim 3

, further comprising repeatedly alternating supplying the first chemistry and supplying the second chemistry until a dielectric layer forms having a thickness between about 10 Å

and 200 Å

.

5. The method of

claim 3

, further comprising supplying a carrier gas while repeatedly alternating supplying the first chemistry and supplying the second chemistry.

6. The method of

claim 5

, wherein the carrier gas purges reactants between supplying the first chemistry and supplying the second chemistry.

7. The method of

claim 6

, wherein supplying the first chemistry is stopped and the reaction chamber is purged with more than about two chamber volumes of purge gas before supplying the second chemistry.

8. The method of

claim 1

, wherein depositing the dielectric layer further comprises exposing the second material to a third reactant species to leave no more than about one monolayer of a third material.

9. The method of

claim 8

, wherein the dielectric layer comprises two different metals and oxygen.

10. The method of

claim 9

, wherein the dielectric layer comprises a metal, silicon and oxygen.

11. The method of

claim 1

, wherein the dielectric layer has a dielectric constant of greater than about 10.

12. The method of

claim 11

, wherein the dielectric layer is selected from the group consisting of aluminum oxide, tantalum oxide, titanium oxide, zirconium oxide, niobium oxide, hafnium oxide, silicon oxide and mixtures and compounds thereof.

13. The method of

claim 11

, wherein the dielectric layer has a dielectric constant equal to or greater than about 20.

14. The method of

claim 1

, wherein the first material is self-terminated.

15. The method of

claim 14

, wherein the first material is terminated by halide ligands.

16. The method of

claim 15

, wherein the first reactant species comprises a zirconium halide and the second reactant species comprises an oxygen-containing source gas.

17. The method of

claim 14

, wherein the first material is terminated by organic ligands.

18. The method of

claim 1

, wherein the first material comprises methyl-terminated aluminum and the second reactant species comprises an oxygen-containing source gas.

19. The method of

claim 1

, wherein the first material comprises ethoxide-terminated tantalum and the second reactant species comprises an oxygen-containing source gas.

20. The method of

claim 1

, further comprising forming a barrier layer directly on the textured silicon surface prior to forming no more than about one monolayer.

21. The method of

claim 20

, wherein forming a barrier layer comprises nitriding the textured silicon surface.

22. The method of

claim 20

, wherein forming a barrier layer comprises oxidizing the textured silicon surface to form a silicon oxide and nitriding the silicon oxide.

23. The method of

claim 1

, wherein bottom electrode conforms to a three-dimensional folding structure.

24. The method of

claim 23

, wherein the bottom electrode conforms to a trench within a semiconductor substrate.

25. The method of

claim 23

, wherein the three-dimensional folding shape is formed above a semiconductor substrate.

26. The method of

claim 25

, wherein the three-dimensional shape defines an interior volume.

27. The method of

claim 26

, wherein the three-dimensional shape conforms to a cylinder.

28. The method of

claim 1

, further comprising depositing a conductive layer over the dielectric layer, wherein depositing the conductive layer comprises:

forming no more than about one monolayer of a third material over the dielectric layer by exposure to a third reactant species; and

reacting a fourth reactant species with the third material to leave no more than about one monolayer of a fourth material.

29. The method of

claim 28

, wherein the third reactant species comprises a metal complex, the fourth reactant species comprises a nitrogen-containing source gas, and the conductive layer comprises a metal nitride.

30. A method of forming a dielectric layer having a dielectric constant greater than about 10 over a textured bottom electrode in an integrated circuit, comprising:

forming no more than about one monolayer of a metal-containing species in a self-limited reaction; and

reacting an oxygen-containing species with the monolayer.

31. The method of

claim 30

, wherein the textured bottom electrode comprises silicon.

32. The method of

claim 31

, wherein the textured bottom electrode has a hemispherical grain morphology.

33. The method of

claim 30

, wherein the self-limited reaction comprises forming a halogen-terminated metal film.

34. The method of

claim 33

, wherein reacting the oxygen-containing species comprises a ligand-exchange reaction.

35. The method of

claim 30

, further comprising repeating forming no more than about one monolayer and reacting the oxygen-containing species at least about 10 times until the dielectric layer has a desired thickness.

36. A capacitor structure in an integrated circuit, comprising;

a bottom electrode conforming to a macrostructural three-dimensional folding shape and a having a textured silicon surface;

a capacitor dielectric having a dielectric constant greater than about 10 conforming to the textured surface, the dielectric having a maximum thickness of less than about 100 Å and

a minimum thickness greater than about 95% of the maximum thickness.

37. The structure of

claim 36

, further comprising a top electrode conforming to the dielectric, the top electrode continuously contacting the dielectric over the entire textured surface.

38. The structure of

claim 37

, wherein the top electrode comprises a conductive barrier layer continuously contacting the dielectric over the entire textured surface and a more conductive material formed over the conductive barrier layer.

39. The structure of

claim 37

, wherein the top electrode comprises an elemental metal layer continuously contacting the dielectric over the entire textured surface.

40. The structure of

claim 36

, wherein the capacitor dielectric comprises a metal oxide.

41. The structure of

claim 40

, wherein the metal oxide comprises aluminum oxide.

42. The structure of

claim 40

, wherein the metal oxide comprises an oxide of a transition metal.

43. The structure of

claim 42

, further comprising a conformal barrier layer formed between the textured silicon layer and the dielectric.

44. The structure of

claim 42

, wherein the metal oxide layer comprises an oxide of a Group IV transition metal.

45. The structure of

claim 42

, wherein the metal oxide comprises an oxide of a Group V transition metal.

46. The structure of

claim 36

, wherein the dielectric comprises a ternary material.

47. The structure of

claim 46

, wherein the dielectric comprises a metal, silicon and oxygen.

48. The structure of

claim 36

, wherein the dielectric has a thickness between about 25 Å

and 100 Å

.

49. The structure of

claim 36

, wherein the minimum thickness is at least about 98% of the maximum thickness.

50. An integrated circuit having a plurality of memory cells, each memory cell including a capacitor comprising:

a first electrode having a surface conforming to a hemispherical grain morphology;

a capacitor dielectric layer adjacent to the first electrode and conforming to the hemispherical grain morphology, the capacitor dielectric comprising a material selected from the group consisting of aluminum oxide, titanium oxide, zirconium oxide, niobium oxide, hafnium oxide, silicon oxide and mixtures and compounds thereof; and

a second electrode adjacent to and conforming to the hemispherical grain morphology.

51. The integrated circuit of

claim 50

, wherein the capacitor dielectric layer has a thickness between about 10 Å

and 200 Å

.

52. The integrated circuit of

claim 50

, wherein the capacitor dielectric layer has a maximum thickness over the first electrode and a minimum thickness over the first electrode no more than about 95% of the maximum thickness.

53. The integrated circuit of

claim 50

, wherein the capacitor dielectric layer further comprises a plurality of sublayers.

54. The integrated circuit of

claim 53

, wherein the sublayers comprise a plurality of sublayers of a first metal oxide alternated with the sublayers of an other metal oxide.

55. A process of forming a capacitor dielectric over a hemispherical grain silicon surface, comprising:

coating the hemispherical grain silicon surface with no more than about one monolayer of a ligand-terminated metal complex in a first phase;

replacing ligands of the ligand-terminated metal with oxygen in a second phase distinct from the first phase; and

repeating the first and second phases in at least about 10 cycles.

56. The process of

claim 55

, wherein each cycle comprises a third phase, the third phase comprising adsorbing no more than about one monolayer of a second ligand-terminated metal after the second phase.

57. The process of

claim 56

, wherein each cycle further comprises a fourth phase, the fourth phase comprising replacing ligands of the second ligand-terminated metal with oxygen.

58. The process of

claim 57

, wherein the first phase comprises pulsing a first oxygen-containing species.

59. The process of

claim 58

, wherein the fourth phase comprises pulsing a different oxygen-containing species.

60. The process of

claim 55

, wherein the ligand-terminated metal comprises a metal ethoxide complex.

61. The process of

claim 55

, wherein the ligand-terminated metal comprises a metal chloride complex.

62. The process of

claim 55

, comprising maintaining a temperature of less than about 350°

C.

63. A method of forming a capacitor with high surface area in an integrated circuit, comprising:

forming a bottom electrode in a three-dimensional folding shape;

superimposing a textured morphology over the three-dimensional folding shape; and

depositing a layer conformally over the textured morphology by cyclically supplying at least two alternating, self-terminating chemistries, the layer forming part of the capacitor .

64. The method of

claim 63

, wherein the layer comprises a capacitor dielectric in direct contact with the bottom electrode.

65. The method of

claim 63

, wherein the layer comprises a thin conductive layer overlying a capacitor dielectric, where the capacitor dielectric directly contacts the bottom electrode.

66. The method of

claim 65

, wherein the bottom electrode comprises a hemispherical grain silicon layer.