Clock control circuit and clock control method

• US 20010026179A1
• Filed: 03/23/2001
• Published: 10/04/2001
• Est. Priority Date: 03/24/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Saeki, Takanori
• Granted Patent: US 6,380,774 B2
• Time in Patent Office: Days
• US Class Current: 327/147
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 5/156 Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Abstract

A clock control circuit which includes a frequency multiplying interpolator for generating and outputting multiphase clocks by frequency multiplying an input clock; a switch for outputting two of the multiphase clocks input thereto from the frequency multiplying interpolator; a fine adjusting interpolator, to which the two outputs from the switch are applied, for outputting a signal obtained by internally dividing the phase difference between the two outputs; and a control circuit for controlling the switching of the switch and varying the internal-division ratio of the fine adjusting interpolator.

Claims

1. A clock control circuit comprising:

a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating a plurality of frequency-multiplied clocks, which have phases that differ from one another, from an input clock; and

at least one phase adjusting interpolator, to which are input two clocks from among the plurality of frequency-multiplied clocks of different phases output from said frequency multiplying interpolator, for outputting a signal obtained by internally dividing a phase difference between these two clocks.

4. The clock control circuit according to any one of

claims 1

to

3

, wherein said frequency multiplying interpolator includes:

a frequency divider for frequency dividing an input clock and generating multiphase clocks;

a period sensing circuit for sensing the cycle of the input clock; and

a multiphase-clock frequency multiplying circuit, to which the multiphase clocks output from said frequency divider are input, for generating multiphase clocks obtained by frequency multiplying the input clocks;

said multiphase-clock frequency multiplying circuit having;

a plurality of timing-difference dividing circuits each of which is for outputting a signal obtained by dividing a timing difference between two inputs applied thereto; and

a plurality of multiplexing circuits each of which is for multiplexing outputs from two of said timing-difference dividing circuits and outputting a multiplexed signal; and

each of said plurality of timing-difference dividing circuits having;

a timing-difference dividing circuit to which two identical-phase clocks are applied as inputs; and

a timing-difference dividing circuit to which two clocks of mutually adjacent phases are applied as inputs.

5. The clock control circuit according to

claim 4

, wherein said multiphase-clock frequency multiplying circuit has n-phase clocks of first to nth clocks input thereto and includes:

2n-number of timing-difference dividing circuits each of which is for outputting a signal obtained by dividing a timing difference between two inputs applied thereto, wherein a (21-1) th (where 1≦

I≦

n holds) timing-difference dividing circuit has Ith identical clocks applied thereto as said two inputs, and a 2Ith (where 1≦

I≦

n holds) timing-difference dividing circuit has an Ith clock and a (I+1 mod n) th (where mod represents residue calculation and I+1 mod n is the reminder obtained when I+1 is divided by n) clock applied thereto as said two inputs;

2n-number of pulse-width correction circuits to which an output of a Jth (where 1≦

J≦

2n holds) timing-difference dividing circuit and an output of a (J+2 mod n) th (where J+2 mod n represents the remainder obtained when J+2 is divided by n) timing-difference dividing circuit are input; and

n-number of multiplexing circuits to which an output of a Kth (where 1≦

K≦

n holds) pulse-width correction circuit and an output of a (K+n) th pulse-width correction circuit are input.

6. The clock control circuit according to

claim 4

, wherein each of said timing-difference dividing circuits includes:

a NOR gate to which first and second input signals are applied; and

an inverter to which the potential of an internal node, which is an output of said NAND gate, is input;

a plurality of series circuits of serially connected switch elements and capacitors being connected in parallel between the internal node and ground; and

capacitance applied to the internal node being decided by a cycle control signal connected to a control terminal of each of said switch elements.

7. The clock control circuit according to

claim 4

, wherein each of said timing-difference dividing circuits includes:

a logic circuit, to which first and second input signals are applied, for outputting result of a predetermined logical operation between the first and second input signals;

a first switch element connected between a first power supply and an internal node and having an output signal of said logic circuit input to a control terminal thereof;

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses;

a first constant-current source and a second switch element, which is turned on and off by the first input signal, connected in series between the internal node and a second power supply; and

a second constant-current source and a third switch element, which is turned on and off by the second input signal, connected in series between the internal node and the second power supply;

a plurality of series circuits of serially connected fourth switch elements and capacitors being connected in parallel between the internal node and the second power supply;

capacitance applied to the internal node being decided by a cycle control signal supplied to a control terminal of each of said fourth switch elements.

8. The clock control circuit according to

claim 7

, wherein said first switch element comprises a transistor of a first conductivity type, and each of said second to fourth switch elements comprises a transistor of a second conductivity type.

9. The clock control circuit according to

claim 4

, wherein each of said timing-difference dividing circuits includes:

a logic circuit, to which first and second input signals are applied, for outputting result of a predetermined logical operation between the first and second input signals;

a P-channel MOS transistor connected between a first power supply and an internal node and having an output signal of said logic circuit applied thereto as a gate input;

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses; and

N-channel MOS transistors connected between the internal node and ground and each having a signal obtained by inverting the first input signal applied thereto as a gate input and each being driven by a constant-current source, and N-channel MOS transistors connected between the internal node and ground and each having a signal obtained by inverting the second input signal applied thereto as a gate input and each being driven by a constant-current source;

a plurality of series circuits of serially connected switch elements and capacitors being connected in parallel between the internal node and ground;

capacitance applied to the internal node being decided by a cycle control signal supplied to a control terminal of each of said switch elements.

10. The clock control circuit according to

claims 1

to

3

, wherein said phase adjusting interpolator includes:

a logic circuit, to which first and second input signals are applied, for outputting result of a predetermined logical operation between the first and second input signals;

a first switch element connected between a first power supply and an internal node and having an output signal of said logic circuit input to a control terminal thereof; and

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses;

a plurality of series circuits being connected in parallel between the internal node and a second power supply, each of said series circuits comprising a first constant-current source, a second switch element turned on and off by the first input signal and a third switch element turned on and off by a control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and the second power supply, each of said series circuits comprising a second constant-current source, a fourth switch element turned on and off by the second input signal and a fifth switch element turned on and off by the control signal from the control circuit;

a plurality of series circuits being connected in parallel between the internal node and the second power supply, each of said series circuits comprising a sixth switch element and a capacitor;

capacitance applied to the internal node being decided by turning on and off the sixth switch element by a cycle control signal connected to a control terminal of said sixth switch element.

11. The clock control circuit according to

claim 10

, wherein said first switch element comprises a transistor of a first conductivity type, and each of said second to fourth switch elements comprises a transistor of a second conductivity type.

12. The clock control circuit according to

claim 10

, wherein at least a prescribed number (N) of each of said second, third, fourth and fifth switches is provided;

K-number (where K is 0 to N) of said third switch elements are turned on by the control signal supplied to said third switch elements;

(N-K)-number of said fifth switch elements are turned on by the control signal supplied to said fifth switch elements;

a signal corresponding to a phase obtained by internally dividing a timing difference between the first and second input signals based upon K in increments of 1/N of the timing difference is output, and the internal-division ratio is varied by varying the value of K.

13. The clock control circuit according to any one of

claims 1

to

3

, wherein said phase adjusting interpolator includes:

an OR gate to which first and second input signals are applied;

a P-channel MOS transistor connected between a power supply and an internal node and having an output signal of said OR gate applied thereto as a gate input;

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses; and

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising an N-channel MOS transistor that has the first input signal applied thereto as a gate input and that is driven by a constant-current source, and a switch element turned on and off by a control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising an N-channel MOS transistor that has the second input signal applied thereto as a gate input and that is driven by a constant-current source, and a switch element turned on and off by the control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising a switch element and a capacitor;

capacitance applied to the internal node being decided by a cycle control signal connected to a control terminal of said switch element.

14. The clock control circuit according to any one of

claims 1

to

3

, wherein said phase adjusting interpolator includes:

a NOR gate to which first and second input signals are applied;

a P-channel MOS transistor connected between a power supply and an internal node and having an output signal of said NOR gate applied thereto as a gate input;

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses; and

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising an N-channel MOS transistor having a signal obtained by inverting the first input signal by a first inverting circuit applied thereto as a gate input and being driven by a constant-current source, and a switch element turned on and off by a control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising an N-channel MOS transistor having a signal obtained by inverting the second input signal by a second inverting circuit applied thereto as a gate input and being driven by a constant-current source, and a switch element turned on and off by the control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising a switch element and a capacitor;

capacitance applied to the internal node being decided by a cycle control signal connected to a control terminal of said switch element.

15. The clock control circuit according to

claims 6

to

9

, wherein the cycle control signal is supplied by said period sensing circuit set forth in

claim 4

.

40. A semiconductor integrated circuit device having a clock control circuit defined in

claims 1

to

19

.

42. The clock control circuit according to

claim 4

, wherein each of said timing-difference dividing circuits includes:

a logic circuit, to which first and second input signals are applied, for outputting result of a predetermined logical operation between the first and second input signals;

an N-channel MOS transistor connected between a first power supply and an internal node and having an output signal of said logic circuit applied thereto as a gate input;

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses; and

P-channel MOS transistors connected between the internal node and ground and each having a signal obtained by inverting the first input signal applied thereto as a gate input and each being driven by a constant-current source, and P-channel MOS transistors connected between the internal node and ground and each having a signal obtained by inverting the second input signal applied thereto as a gate input and each being driven by a constant-current source;

a plurality of series circuits of serially connected switch elements and capacitors being connected in parallel between the internal node and ground;

capacitance applied to the internal node being decided by a cycle control signal supplied to a control terminal of each of said switch elements.

43. The clock control circuit according to any one of

claims 1

to

3

, wherein said phase adjusting interpolator includes:

an OR gate to which first and second input signals are applied;

a N-channel MOS transistor connected between a power supply and an internal node and having an output signal of said OR gate applied thereto as a gate input;

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses; and

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising an P-channel MOS transistor that has the first input signal applied thereto as a gate input and that is driven by a constant-current source, and a switch element turned on and off by a control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising an P-channel MOS transistor that has the second input signal applied thereto as a gate input and that is driven by a constant-current source, and a switch element turned on and off by the control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising a switch element and a capacitor;

capacitance applied to the internal node being decided by a cycle control signal connected to a control terminal of said switch element.

44. The clock control circuit according to any one of

claims 1

to

3

, wherein said phase adjusting interpolator includes:

a NOR gate to which first and second input signals are applied;

a N-channel MOS transistor connected between a power supply and an internal node and having an output signal of said NOR gate applied thereto as a gate input;

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses; and

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising an P-channel MOS transistor having a signal obtained by inverting the first input signal by a first inverting circuit applied thereto as a gate input and being driven by a constant-current source, and a switch element turned on and off by a control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising an P-channel MOS transistor having a signal obtained by inverting the second input signal by a second inverting circuit applied thereto as a gate input and being driven by a constant-current source, and a switch element turned on and off by the control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and ground, each of said series circuits comprising a switch element and a capacitor;

capacitance applied to the internal node being decided by a cycle control signal connected to a control terminal of said switch element.

2. A clock control circuit comprising:

(a) a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating multiphase clocks obtained by frequency multiplying an input clock;

(b) a switch, to which the multiphase clocks output from said frequency multiplying interpolator are input, for selectively outputting at least a pair of clocks from among the multiphase clocks;

(c) at least one phase adjusting interpolator, to which the pair of clocks output from said switch is input, for outputting a signal obtained by internally dividing a phase difference between the pair of clocks; and

(d) a control circuit for controlling a setting of an internal-division ratio of said phase adjusting interpolator and switching of a clock output by said switch.

16. The clock control circuit according to

claim 2

or

3

, wherein if a setting of the internal-division ratio of said phase adjusting interpolator reaches an upper limit or lower limit and it is still necessary to perform an adjustment of output phase in said phase adjusting interpolator, then said control circuit changes over the clock output of said switch that selectively outputs clocks supplied to said phase adjusting interpolator.

17. The clock control circuit according to

claim 2

or

3

, wherein said control circuit controls setting of the internal-division ratio of said phase adjusting interpolator and switching of the clock output of said switch based upon result of a phase comparison between the input clock or a predetermined reference clock and the output of said phase adjusting interpolator.

18. The clock control circuit according to

claim 2

or

3

, wherein said control circuit has a counter the value of which varies based upon result of a phase comparison between the input clock or a predetermined reference clock and the output of said phase adjusting interpolator;

setting of the internal-division ratio of said phase adjusting interpolator and switching of the clock output of said switch being controlled based upon an output from said counter.

19. The clock control circuit according to

claim 2

or

3

, wherein said control circuit includes:

a counter the value of which varies based upon result of a phase comparison between the input clock or a predetermined reference clock and the output of said phase adjusting interpolator; and

a decoder for decoding an output from said counter;

setting of the internal-division ratio of said phase adjusting interpolator and switching of the clock output of said switch being control led based upon an output from said decoder.

20. The clock control circuit according to

claim 2

or

3

, wherein said switch comprises a rotary switch in which, if an n-phase clock output from said frequency multiplying interpolator is input thereto and, on the basis of a switching control signal from said control circuit, an l-th clock is being supplied to a first input of said phase adjusting interpolator and an adjacent (I+1) th clock is being supplied to a second input of said phase adjusting interpolator, then, when the clock output is switched in accordance with a phase-lag or phase-lead state of the output, said rotary circuit controls switching in such a manner that the first input of said phase adjusting interpolator is made an (I+2) th clock and the second input is kept as the (I+1 th clock, or the first input is kept at the Ith clock and the second input is made the (I−

1) th clock (where I+1, I−

1, I+2 take on values of 1 to n and are given by a remainder obtained by dividing by n).

3. A clock control circuit comprising:

(a) a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating multiphase clocks obtained by frequency multiplying an input clock;

(b) one or a plurality of switches, to which the multiphase clocks output from said frequency multiplying interpolator are input, for outputting pairs of clocks of combinations selected from among the multiphase clocks;

(c) a plurality of phase adjusting interpolators, to respective ones of which the plurality of pairs of clocks selectively output from said switch are input, for outputting signals obtained by internally dividing a phase difference between each pair of clocks; and

(d) a control circuit for controlling a setting of an internal-division ratio of each of said phase adjusting interpolators and switching of a clock output by said switch.

21. An interpolator comprising:

a logic circuit, to which first and second input signals are applied, for outputting result of a predetermined logical operation between the first and second input signals;

a first switch element connected between a first power supply and an internal node and having an output signal of said logic circuit input to a control terminal thereof; and

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses;

a plurality of series circuits being connected in parallel between the internal node and a second power supply, each of said series circuits comprising a first constant-current source, a second switch element turned on and off by the first input signal and a third switch element turned on and off by a control signal applied to a control terminal thereof;

a plurality of series circuits being connected in parallel between the internal node and the second power supply, each of said series circuits comprising a second constant-current source, a fourth switch element turned on and off by the second input signal and a fifth switch element turned on and off by a control signal applied to a control terminal thereof;

a plurality of series circuits being connected in parallel between the internal node and the second power supply, each of said series circuits comprising a sixth switch element and a capacitor;

capacitance applied to the internal node being decided by turning on and off the sixth switch element by a cycle control signal applied to a control terminal thereof;

an output signal corresponding to a phase obtained by internally dividing a phase difference between the first input signal and the second input signal being delivered from said buffer circuit in dependence upon a combination of values of the control signals applied to the control terminals of said third switch elements and to the control terminals of said fifth switch elements.

22. The interpolator according to

claim 21

, wherein at least a prescribed number (N) of each of said second, third, fourth and fifth switches is provided;

K-number (where K is 0 to N) of said third switch elements are turned on by the control signal supplied to said third switch elements;

(N-K)-number of said fifth switch elements are turned on by the control signal supplied to said fifth switch elements;

a signal corresponding to a phase obtained by internally dividing a timing difference between the first and second input signals based upon K in increments of 1/N of the timing difference is output, and the internal-division ratio is varied by varying the value of K.

23. A clock control method comprising the steps of:

reducing jitter of a frequency-multiplied clock by generating multiphase clocks, which are obtained by frequency multiplying an input clock, using a frequency multiplying interpolator which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals;

selecting two of the multiphase clocks, which are output from the frequency multiplying interpolator, by a switch and supplying the two clocks to a phase adjusting interpolator;

outputting from said phase adjusting interpolator a clock obtained by internally dividing a phase difference between the two clocks; and

performing control to vary an internal-division ratio of the phase adjusting interpolator based upon result of a phase comparison between a predetermined reference clock and an output clock of the phase adjusting interpolator.

24. A clock control method using first, second and third interpolators each of which outputs a signal obtained by internally dividing a phase difference between two signals input thereto, said method comprising the steps of:

inputting a common data signal, which is transferred in sync with a clock signal, to said first interpolator for delaying the data signal and then outputting the same;

inputting the clock signal to said second interpolator for outputting a clock signal obtained by internally dividing a timing difference between a leading edge and a trailing edge of a clock pulse;

inputting the clock signal to said third interpolator for outputting a clock signal obtained by internally dividing a timing difference between a trailing edge of the clock pulse and a leading edge of an ensuing clock pulse; and

latching data that is output from said first interpolator using a clock, which is obtained by multiplexing output signals from said second and third interpolators, as a latch timing pulse, and automatically adjusting latch timing to an optimum position with respect to the data independently of a fluctuation in duty of the clock signal.

25. A clock control circuit comprising:

a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;

a plurality of switches, to which the multiphase clocks output from said frequency multiplying interpolator are input, for selecting and outputting pairs of clocks;

a plurality of interpolators, to respective ones of which the pairs of clocks output from said switch are input, for outputting signals obtained by internally dividing a phase difference between respective ones of the pairs of clocks; and

a control circuit for controlling a setting of an internal-division ratio of each of said interpolators and switching of a clock output by each of said switches;

a clock output from one of said interpolators being adjusted in phase so as to have a predetermined phase difference with respect to the input clock, and clocks output from the other of said interpolators being adjusted in phase so as to have a predetermined phase difference with respect to the input clock or with respect to an output clock of Yet another interpolator.

26. A clock control circuit comprising:

a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;

first and second switches, to which the multiphase clocks output from said frequency multiplying interpolator are input for selecting and outputting pairs of clocks;

a first interpolator, to which the pair of clocks output from said first switch is input, for outputting a clock signal obtained by internally dividing a phase difference between the pair of clocks and applying a phase adjustment;

a second interpolator, to which the pair of clocks output from said second switch is input, for outputting a clock signal obtained by internally dividing a phase difference between the pair of clocks and applying a phase adjustment;

a phase comparator circuit for detecting a phase difference between an output of said first interpolator and the input clock;

a filter for smoothing a signal representing the result of the phase comparison output from said phase comparator circuit;

a first counter for counting up and counting down based upon the signal representing the result of the phase comparison output from said filter; and

a second counter, which is set to an offset value, for counting up and counting down based upon the signal representing the result of the phase comparison output from said filter;

setting of an internal-division ratio of said first interpolator and switching of a clock output by said first switch being performed based upon an output from said first counter; and

setting of an internal-division ratio of said second interpolator and switching of a clock output by said second switch being performed based upon an output from said second counter.

30. The clock control circuit according to

claim 26

or

27

, wherein each of said first and second switches selects and outputs, from among the multiphase clocks output from said multiphase clock generating circuit, a first pair of signals, which comprises a first signal and a second signal having a phase adjacent that of the first signal, and a second pair of signals, which comprises a third signal having a predetermined phase difference with respect to the first signal and a fourth signal having a phase adjacent that of the third signal;

each of said first and second interpolators has;

a first phase adjusting interpolator for producing a first output signal obtained by internally dividing a timing difference between the first pair of signals; and

a second phase adjusting interpolator for producing a second output signal obtained by internally dividing a timing difference between the second pair of signals;

said clock control circuit further comprising;

a first multiplexing circuit for multiplexing and outputting the first and second output signals from said first and second phase adjusting interpolators, respectively, of said first interpolator; and

a second multiplexing circuit for multiplexing and outputting the first and second output signals from said first and second phase adjusting interpolators, respectively, of said second interpolator.

33. The clock control circuit according to any one of

claims 26

to

29

, comprising a frequency multiplying interpolator constituted by a multiphase frequency multiplying circuit in which said multiphase clock generating circuit has a plurality of timing-difference dividing circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals from among the multiphase clocks generated from the input clock.

34. The clock control circuit according to any one of

claims 26

to

29

, comprising a frequency multiplying interpolator constituted by a multiphase multiplying circuit wherein said multiphase clock generating circuit includes:

a frequency divider for generating multiphase clocks by frequency dividing an input clock;

a period sensing circuit for sensing the cycle of the input clock; and

a multiphase-clock frequency multiplying circuit, to which the multiphase clocks output from said frequency divider are input, for generating multiphase clocks obtained by frequency multiplying the input clocks;

said multiphase-clock frequency multiplying circuit has;

a plurality of timing-difference dividing circuits each of which is for outputting a signal obtained by dividing a timing difference between two inputs applied thereto; and

a plurality of multiplexing circuits each of which is for multiplexing outputs from two of said timing-difference dividing circuits; and

each of said plurality of timing-difference dividing circuits has;

a timing-difference dividing circuit to which two identical-phase clocks are applied as inputs; and

a timing-difference dividing circuit to which two clocks of mutually adjacent phases are applied as inputs.

35. The clock control circuit according to

claim 34

, wherein said multi phase-clock frequency multiplying circuit has n-phase clocks (first to nth clocks) input thereto and includes:

2n-number of timing-difference dividing circuits each of which is for outputting a signal obtained by dividing a timing difference between two inputs applied thereto, wherein a (21-1) th (where 123 I≦

n holds) timing-difference dividing circuit has Ith identical clocks applied thereto as said two inputs, and a 2Ith (where 1≦

I≦

n holds) timing-difference dividing circuit has an Ith clock and a (I+1 mod n) th (where mod represents residue calculation and I+1 mod n is the residue obtained when I+1 is divided by n) clock applied thereto as said two inputs;

2n-number of pulse-width correction circuits to which an output of a Jth (where 1≦

J≦

2n holds) timing-difference dividing circuit and an output of a (J+2 mod n) th (where J+2 mod n represents the remainder obtained when J+2 is divided by n) timing-difference dividing circuit are input; and

n-number of multiplexing circuits to which an output of a Kth (where 1≦

K≦

n holds) pulse-width correction circuit and an output of a (K+n) th pulse-width correction circuit are input.

36. The clock control circuit according to

claim 34

, wherein each of said timing-difference dividing circuits includes:

a NOR gate to which first and second input signals are applied; and

an inverter to which the potential of an internal node, which is an output of said NAND gate, is input;

a plurality of series circuits of serially connected switch elements and capacitors being connected in parallel between the internal node and ground; and

capacitance applied to the internal node being decided by a cycle control signal connected to a control terminal of each of the switch elements

37. The clock control circuit according to

claim 34

, wherein each of said timing-difference dividing circuits includes:

a logic circuit, to which first and second input signals are applied, for outputting result of a predetermined logical operation between the first and second input signals;

a first switch element connected between a first power supply and an internal node and having an output signal of said logic circuit input to a control terminal thereof;

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses;

a first constant-current source and a second switch element, which is turned on and off by the first input signal, connected between the internal node and a second power supply; and

a second constant-current source and a third switch element, which is turned on and off by the second input signal, connected between the internal node and the second power supply;

a plurality of series circuits being connected in parallel between the internal node and the second power supply, each of said series circuits comprising a fourth switch element and a capacitor;

capacitance applied to the internal node being decided by a cycle control signal supplied to a control terminal of said fourth switch element.

38. A clock control circuit according to any one of

claims 26

to

29

, wherein said phase adjusting interpolator includes:

a logic circuit, to which first and second input signals are applied, for outputting result of a predetermined logical operation between the first and second input signals;

a first switch element connected between a first power supply and an internal node and having an output signal of said logic circuit input to a control terminal thereof; and

a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses;

a plurality of series circuits being connected in parallel between the internal node and a second power supply, each of said series circuits comprising a first constant-current source, a second switch element turned on and off by the first input signal and a third switch element turned on and off by a control signal from said control circuit;

a plurality of series circuits being connected in parallel between the internal node and the second power supply, each of said series circuits comprising a second constant-current source, a fourth switch element turned on and off by the second input signal and a fifth switch element turned on and off by the control signal from the control circuit;

a plurality of series circuits being connected in parallel between the internal node and the second power supply, each of said series circuits comprising a sixth switch element and a capacitor;

capacitance applied to the internal node being decided by turning on and off the sixth switch element by a cycle control signal connected to a control terminal of said sixth switch element.

27. A clock control circuit comprising:

a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;

first and second switches, to which the multiphase clocks output from said frequency multiplying interpolator are input, for selecting and outputting pairs of clocks;

a first interpolator, to which the pair of clocks output from said first switch is input, for outputting a clock signal obtained by internally dividing a phase difference between the pair of clocks and applying a phase adjustment;

a second interpolator, to which the pair of clocks output from said second switch is input, for outputting a clock signal obtained by internally dividing a phase difference between the pair of clocks and applying a phase adjustment;

said second interpolator having an output to which is connected a clock transmission path supplied with a clock;

said first interpolator having an output to which is connected a dummy circuit having a delay time equivalent to that of said clock transmission path;

a phase comparator circuit for detecting a phase difference between an output of said dummy circuit and the input clock;

a filter for smoothing a signal representing the result of the phase comparison output from said phase comparator circuit;

a first counter for counting up and counting down based upon the signal representing the result of the phase comparison output from said filter;

a first decoder for decoding an output count from said first counter;

an adder circuit for adding the output count from said first counter and an input offset value; and

a second decoder for decoding an output from said adder circuit;

setting of an internal-division ratio of said first interpolator and switching of a clock output by said first switch being performed based upon an output from said first decoder; and

setting of an internal-division ratio of said second interpolator and switching of a clock output by said second switch being performed based upon an output from said second decoder.

28. A clock control circuit comprising:

a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;

first, second and third switches, to which the multiphase clocks output from said frequency multiplying interpolator are input, for selecting and outputting pairs of clocks;

first, second and third interpolators, to which the pairs of clocks output from said first, second and third switches, respectively, are input, for outputting clock signals obtained by internally dividing a phase difference between respective ones of the pairs of clocks and applying a phase adjustment;

said third interpolator having an output to which is connected a clock transmission path supplied with a clock;

a first phase comparator circuit for detecting a phase difference between an output of said first interpolator and the input clock;

a first filter for smoothing a signal representing the result of the phase comparison output from said first phase comparator circuit;

a first counter for counting up and counting down based upon the signal representing the result of the phase comparison output from said first filter;

a first decoder for decoding an output count from said first counter;

an adder circuit for adding the output count from said first counter and an input offset value;

a second decoder for decoding an output from said adder circuit;

setting of an internal-division ratio of said first interpolator and switching of a clock output by said first switch being performed based upon a decoded output from said first decoder;

setting of an internal-division ratio of said second interpolator and switching of a clock output by said second switch being performed based upon a decoded output from said second decoder;

a second phase comparator circuit for detecting a phase difference between an output of said clock transmission path and the output of said second interpolator;

a second filter for smoothing a signal representing the result of the phase comparison output from said second phase comparator circuit;

a second counter for counting up and counting down based upon the signal representing the result of the phase comparison output from said second filter; and

a third decoder for decoding an output count from said second counter;

setting of an internal-division ratio of said third interpolator and switching of a clock output by said third switch being performed based upon a decoded output from said third decoder.

31. The clock control circuit according to

claim 28

, wherein each of said first to third switches selects and outputs, from among the multiphase clocks output from said multiphase clock generating circuit, a first pair of signals, which comprises a first signal and a second signal having a phase adjacent that of the first signal, and a second pair of signals, which comprises a third signal having a predetermined phase difference with respect to the first signal and a fourth signal having a phase adjacent that of the third signal;

each of said first and second interpolators has;

a first phase adjusting interpolator for producing a first output signal obtained by internally dividing a timing difference between the first pair of signals; and

a second phase adjusting interpolator for producing a second output signal obtained by internally dividing a timing difference between the second pair of signals;

said clock control circuit further comprising;

first to third multiplexing circuits for multiplexing and outputting the first and second output signals output from said first and second phase adjusting interpolators of respective ones of said first to third interpolators.

29. A clock control circuit comprising:

a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;

first, second, third and fourth switches, to which the multiphase clocks output from said frequency multiplying interpolator are input, for selecting and outputting pairs of clocks;

first, second, third and fourth interpolators, to which the pairs of clocks output from said first, second, third and fourth switches, respectively, are input, for outputting clock signals obtained by internally dividing a phase difference between respective ones of the pairs of clocks and applying a phase adjustment;

said fourth interpolator having an output to which is connected a clock transmission path supplied with a clock;

a first phase comparator circuit for detecting a phase difference between the rising edge of an output of said first interpolator and the rising edge of the input clock;

a first filter for smoothing a signal representing the result of the phase comparison output from said first phase comparator circuit;

a first counter for counting up and counting down based upon the signal representing the result of the phase comparison output from said first filter;

a second phase comparator circuit for detecting a phase difference between an output of said clock transmission path and the falling edge of a signal obtained by inverting the input clock by an inverting circuit;

a second filter for smoothing a signal representing the result of the phase comparison output from said second phase comparator circuit;

a second counter for counting up and counting down based upon the signal representing the result of the phase comparison output from said second filter;

an averaging circuit for averaging an output count from said first counter and an output count of said second counter;

a first decoder for decoding an output from said first counter;

a second decoder for decoding an output from said second counter;

a third decoder for decoding an output from said averaging circuit;

setting of an internal-division ratio of each of said first to third interpolators and switching of a clock output by each of said first to third switches being performed based upon a decoded output from each of said first to third decoders;

a third phase comparator circuit for detecting a phase difference between an output of said clock transmission path and the output of said third interpolator;

a third filter for smoothing a signal representing the result of the phase comparison output from said third phase comparator circuit;

a third counter for counting up and counting down based upon the signal representing the result of the phase comparison output from said third filter; and

a fourth decoder for decoding an output count from said third counter;

setting of an internal-division ratio of said fourth interpolator and switching of a clock output by said fourth switch being performed based upon a decoded output from said fourth decoder.

32. The clock control circuit according to

claim 29

, wherein each of said first to fourth switches selects and outputs, from among the multiphase clocks output from said multiphase clock generating circuit, a first pair of signals, which comprises a first signal and a second signal having a phase adjacent that of the first signal, and a second pair of signals, which comprises a third signal having a predetermined phase difference with respect to the first signal and a fourth signal having a phase adjacent that of the third signal;

each of said first and second interpolators has;

a first phase adjusting interpolator for producing a first output signal obtained by internally dividing a timing difference between the first pair of signals; and

a second phase adjusting interpolator for producing a second output signal obtained by internally dividing a timing difference between the second pair of signals;

said clock control circuit further comprising;

first to fourth multiplexing circuits for multiplexing and outputting the first and second output signals output from said first and second phase adjusting interpolators of respective ones of said first to fourth interpolators.

39. A clock control circuit comprising:

first, second and third interpolators each of which is for outputting a signal obtained by internally dividing a phase difference between two signals input thereto;

a common data signal being input to said first interpolator for being delayed and then output thereby;

a clock signal being input to said second interpolator, and said second interpolator outputting a clock signal obtained by internally dividing a timing difference between a leading edge and a trailing edge of a clock pulse;

said third interpolator outputting a clock signal obtained by internally dividing a timing difference between a trailing edge of the clock pulse and a leading edge of an ensuing clock pulse of the clock signal; and

a multiplexing circuit for multiplexing the output clocks from said second and third interpolators and outputting a clock signal;

the clock signal output from said multiplexing circuit being supplied to a latch circuit as a latch timing clock for latching data that is output from said first interpolator.

41. A semiconductor integrated circuit device having a plurality of macroblocks, said device comprising:

a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating and outputting multiphase clocks obtained by frequency multiplying an input clock;

each of said macroblocks having a switch, to which the multiphase clocks output from said frequency multiplying interpolator are input, for outputting at least two clocks from among the multiphase clocks, and a phase adjusting interpolator, to which an output from said switch is input, for outputting a signal obtained by internally dividing the phase of said output; and

a control circuit for controlling switching of the clock by said switch and varying an internal-division ratio of said phase adjusting interpolator.