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Clock control circuit and clock control method

  • US 20010026179A1
  • Filed: 03/23/2001
  • Published: 10/04/2001
  • Est. Priority Date: 03/24/2000
  • Status: Active Grant
First Claim
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1. A clock control circuit comprising:

  • a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating a plurality of frequency-multiplied clocks, which have phases that differ from one another, from an input clock; and

    at least one phase adjusting interpolator, to which are input two clocks from among the plurality of frequency-multiplied clocks of different phases output from said frequency multiplying interpolator, for outputting a signal obtained by internally dividing a phase difference between these two clocks.

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