Low voltage power MOSFET device and process for its manufacture

• US 20010026989A1
• Filed: 03/21/2001
• Published: 10/04/2001
• Est. Priority Date: 04/04/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Thapar, Naresh
• Granted Patent: US 6,580,123 B2
• Time in Patent Office: Days
• US Class Current: 438/400
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low R_DSON and increased V_DSMAX and V_GSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 Å to 1400 Å and the nitride is subsequently removed and a thin oxide, for example 320 Å is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon. A very lightly doped diffusion of 1000 Å to 2000 Å in depth could also be formed around the bottom of the trench and is depleted at all times by the inherent junction voltage to further reduce Miller capacitance and switching loss.

Claims

1. A trench type MOSgated power semiconductor device comprising a wafer of silicon of one conductivity type;

a plurality of spaced trenches formed into the top surface of said wafer and extending therein to a given depth;

an insulation coating lining the side walls and bottom of said trench;

a conductive gate body filling the interior of each of said trenches;

a channel region of a second conductivity type extending into the top of said wafer to a first depth which is less than said given depth;

a source region of said one conductivity type extending into said channel region to a first depth from the top of said wafer to define invertable channels along the sides of said trench in said channel region which extends between said first and second depths;

a source electrode formed on the top surface of said wafer and connected to said source and channel regions;

a drain electrode connected to the bottom of said wafer; and

a shallow diffusion of the second conductivity type surrounding the bottom of each of said trenches, said shallow diffusion having a concentration substantially less than that of said channel region and being at all times depleted by the built-in junction voltage at its junction to the surrounding one conductivity type material of said wafer.

2. The device of

claim 1

wherein said one conductivity type is the N type and said second conductivity type is the P type.

3. The device of

claim 1

wherein said wafer has an epitaxially deposited layer of said one conductivity type extending from the top of said wafer and receiving said trenches and said channel and source regions.

4. The device of

claim 1

wherein said insulation coating is silicon dioxide.

5. The device of

claim 1

wherein said insulation coating in said side walls has a thickness of about 320 Å

and said insulation coating on the bottom of said trench having a thickness greater than about 1000 Å and

having a positively curved bottom surface without sharp corners.

6. The device of

claim 1

wherein said conductive gate body is a conductive polysilicon.

7. The device of

claim 1

wherein said trenches have a topology selected from the group consisting of symmetrically distributed vertical cells and parallel extending vertical stripes.

8. The device of

claim 3

wherein said one conductivity type is the N type and said second conductivity type is the P type.

9. The device of

claim 4

wherein said one conductivity type is the N type and said second conductivity type is the P type.

10. The device of

claim 5

wherein said one conductivity type is the N type and said second conductivity type is the P type.

11. The device of

claim 6

wherein said one conductivity type is the N type and said second conductivity type is the P type.

12. The device of

claim 8

wherein said insulation coating is silicon dioxide.

13. The device of

claim 12

wherein said insulation coating in said side walls has a thickness of about 320 Å

and said insulation coating on the bottom of said trench having a thickness greater than about 1000 Å and

having a positively curved bottom surface without sharp corners.

14. The device of

claim 13

wherein said conductive gate body is a conductive polysilicon.

15. The device of

claim 1

wherein the vertical distance between said first and second depth is about 0.7 microns.

16. The device of

claim 15

wherein said source region is formed by an implant and subsequent diffusion process which produces implant damage to a third depth;

said source region second depth being greater than said third depth, whereby said invertable channel regions are formed in undamaged silicon for their full lengths.

17. A trench type MOSgated power semiconductor device comprising a wafer of silicon of one conductivity type;

a plurality of spaced trenches formed into the top surface of said wafer and extending therein to a given depth;

an insulation coating lining the side walls and bottom of said trench;

a conductive gate body filling the interior of each of said trenches;

a channel region of a second conductivity type extending into the top of said wafer to a first depth which is less than said given depth;

a source region of said one conductivity type extending into said channel region to a first depth from the top of said wafer to define invertable channels along the sides of said trench in said channel region which extends between said first and second depths;

a source electrode formed on the top surface of said wafer and connected to said source and channel regions;

a drain electrode connected to the bottom of said wafer; and

said first and second depths being vertically separated by about 0.7 microns.

18. The device of

claim 17

wherein said source region is formed by an implant and subsequent diffusion process which produces implant damage to a third depth;

and said source region second depth being greater than said third depth, whereby said invertable channel regions are formed in undamaged silicon for their full lengths.

19. The device of

claim 17

wherein said insulation coating on the bottom of said trench have a thickness greater than about 1000 Å

and having a positively curved bottom surface without sharp corners.

20. The device of

claim 17

wherein said one conductivity type is the N type and said second conductivity type is the P type.

21. The device of

claim 17

wherein said wafer has an epitaxially deposited layer of said one conductivity type extending from the top of said wafer and receiving said trenches and said channel and source regions.

22. The device of

claim 17

wherein said insulation coating is silicon dioxide.

23. The device of

claim 17

wherein said conductive gate body is a conductive polysilicon.

24. The device of

claim 17

wherein said trenches have a topology selected from the group consisting of symmetrically distributed vertical cells and parallel extending vertical stripes.

25. A trench type MOSgated power semiconductor device comprising a wafer of silicon of one conductivity type;

a plurality of spaced trenches formed into the top surface of said wafer and extending therein to a given depth;

an insulation coating lining the side walls and bottom of said trench;

a conductive gate body filling the interior of each of said trenches;

a channel region of a second conductivity type extending into the top of said wafer to a first depth which is less than said given depth;

a source region of said one conductivity type extending into said channel region to a first depth from the top of said wafer to define invertable channels along the sides of said trench in said channel region which extends between said first and second depths;

a source electrode formed on the top surface of said wafer and connected to said source and channel regions;

a drain electrode connected to the bottom of said wafer;

said insulation coating on said side walls having a thickness of about 320 Å

;

said insulation coating on the bottom of said trench having a thickness greater than about 1000 Å and

having a positively curved bottom surface without sharp corners.

26. The device of

claim 25

wherein said one conductivity type is the N type and said second conductivity type is the P type.

27. The device of

claim 25

wherein said wafer has an epitaxially deposited layer of said one conductivity type extending from the top of said wafer and receiving said trenches and said channel and source regions.

28. The device of

claim 25

wherein said insulation coating is silicon dioxide.

29. The device of

claim 25

wherein said conductive gate body is a conductive polysilicon.

30. The device of

claim 25

wherein said trenches have a topology selected from the group consisting of symmetrically distributed vertical cells and parallel extending vertical stripes.

31. The device of

claim 25

wherein the vertical distance between said first and second depth is about 0.7 microns.

32. The device of

claim 25

wherein said source region is formed by an implant and subsequent diffusion process which produces implant damage to a third depth;

said source region second depth being greater than said third depth, whereby said invertable channel regions are formed in undamaged silicon for their full lengths.

33. A trench type MOSgated power semiconductor device comprising a wafer of silicon of one conductivity type;

a plurality of spaced trenches formed into the top surface of said wafer and extending therein to a given depth;

an insulation coating lining the side walls and bottom of said trench;

a conductive gate body filling the interior of each of said trenches;

a channel region of a second conductivity type extending into the top of said wafer to a first depth which is less than said given depth;

a source region of said one conductivity type extending into said channel region to a first depth from the top of said wafer to define invertable channels along the sides of said trench in said channel region which extends between said first and second depths;

a source electrode formed on the top surface of said wafer and connected to said source and channel regions;

a drain electrode connected to the bottom of said wafer;

said source region being formed by an implant and subsequent diffusion process which produces implant damage to a third depth; and

said source region second depth being greater than said third depth, whereby said invertable channel regions are formed in undamaged silicon for their full lengths.

34. The device of

claim 33

wherein said one conductivity type is the N type and said second conductivity type is the P type.

35. The device of

claim 33

wherein said wafer has an epitaxially deposited layer of said one conductivity type extending from the top of said wafer and receiving said trenches and said channel and source regions.

36. The device of

claim 33

wherein said insulation coating is silicon dioxide.

37. The device of

claim 33

wherein said insulation coating in said side walls has a thickness of about 320 Å

and said insulation coating on the bottom of said trench having a thickness greater than about 1000 Å and

having a positively curved bottom surface without sharp corners.

38. The device of

claim 33

wherein said conductive gate body is a conductive polysilicon.

39. The device of

claim 33

wherein said trenches have a topology selected from the group consisting of symmetrically distributed vertical cells and parallel extending vertical stripes.

40. The device of

claim 33

wherein the vertical distance between said first and second depth is about 0.7 microns.

41. The process for forming a trench type MOSgated device;

said process comprising the steps of etching a trench having spaced side walls and a bottom surface into a silicon wafer wherein said bottom surface and side walls meet at a sharp angle;

forming a silicon nitride layer on said side walls and said bottom surface;

removing said silicon nitride layer from said bottom surface only;

forming silicon dioxide layer on said trench bottom which has a thickness in excess of 1000 Å

on said bottom surface and rounding said bottom surface and sharp corners while forming said bottom silicon dioxide layer, and thereafter removing the silicon nitride layer on said walls and then forming silicon dioxide layers on said side walls which have a thickness substantially less than 1000 Å

.

42. The process of

claim 41

wherein said silicon dioxide layers on said walls have a thickness of about 320 Å

.

43. In a MOSgated power semiconductor device comprising a drain conductor region of one conductivity type, a source conductive region of said one conductivity type, and a channel conductor region of the opposite conductivity type;

a gate oxide layer extending from said source conductive region, across said channel conductive region and to said drain conductive region and a conductive gate electrode disposed on a surface of said gate oxide and operable to produce an inversion layer in said channel region to permit conduction between said source and drain regions;

the improvement which comprises a shallow, lightly doped diffusion of said opposite conductivity type in said drain conductor region adjacent said gate oxide; and

said shallow diffusion being depleted by the inherent junction voltage of the junction between said shallow diffusion and said drain region.

44. The device of

claim 43

wherein said shallow diffusion has a depth of less than about 2000 Å

.

45. The device of

claim 43

wherein said shallow diffusion has a concentration which is substantially less than the concentration of said channel region.

46. The device of

claim 44

wherein said shallow diffusion has a concentration which is substantially less than the concentration of said channel region.

47. The device of

claim 45

wherein said shallow diffusion is formed by an implant dose of about 1×

10¹² atoms/cm².

48. The device of

claim 43

wherein said device is a trench type MOSFET and wherein said shallow diffusion is formed around the bottom of a trench which receives said gate oxide.

49. The process for forming a trench type MOSgated device;

said process comprising the steps of etching a trench having spaced side walls and a bottom surface into a monocrystalline silicon wafer;

amorphizing the bottom surface of the trench but not its side walls; and

thereafter growing a silicon dioxide layer on the side walls and bottom of the trench, wherein the silicon dioxide layer will be substantially thicker at the bottom of said trench than on the side walls.

50. The process of

claim 49

, wherein the silicon oxide coating on said walls have a thickness of greater than about 1000 Å

.

51. The process of

claim 49

, wherein the step of amorphizing the silicon at the bottom of said trench is carried out by an ion implant of a neutral species into the bottom of said trench.

52. The process of

claim 51

, wherein said ion implant is at a heavy dose of greater than about 1E16 atoms/cm².

53. The process of

claim 52

, wherein the silicon oxide coating on said walls have a thickness of greater than about 1000 Å

.