Merged logic and memory combining thin film and bulk Si transistors
First Claim
1. A plurality of transistors made in two distinct semiconductor levels, a bulk silicon (Si) and a thin film Si level, in a single integrated circuit (IC) chip, and connected to form logic circuits in selected regions of the IC chip and to form static random access memory (SRAM) arrays in the remaining regions of the IC chip.
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Abstract
The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.
278 Citations
16 Claims
- 1. A plurality of transistors made in two distinct semiconductor levels, a bulk silicon (Si) and a thin film Si level, in a single integrated circuit (IC) chip, and connected to form logic circuits in selected regions of the IC chip and to form static random access memory (SRAM) arrays in the remaining regions of the IC chip.
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10. A method of manufacturing a plurality of transistors in two distinct semiconductor levels in an integrated circuit (IC) chip comprising the steps of:
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forming n-type metal oxide semiconductor (NMOS) transistors in a bulk silicon (Si) level;
depositing a thick insulator of the bulk Si level;
planarizing the deposited thick insulator;
forming a thin film (TF) Si level on the planarized thick insulator;
implanting a p-type dopant in the TF Si level; and
forming p-type metal oxide semiconductor (PMOS) transistors in the TF Si level. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification