Super-junction semiconductor device and method of manufacturing the same

• US 20010028083A1
• Filed: 02/09/2001
• Published: 10/11/2001
• Est. Priority Date: 02/09/2000
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Sato, Takahiro, Onishi, Yasuhiko, Iwamoto, Susumu, Nagaoka, Tatsuji, Ueno, Katsunori, Fujihira, Tatsuhiko
• Granted Patent: US 6,724,042 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

Claims

1. A semiconductor device comprising:

a semiconductor chip having a first major surface and a second major surface opposing the first major surface;

an active region on a side of the first major surface;

a layer of a first conductivity type on a side of the second major surface, the layer of the first conductivity type exhibiting relatively low electrical resistance;

a first main electrode electrically connected to the active region;

a second main electrode electrically connected to the layer of the first conductivity type;

a drain drift region between the active region and the layer of the first conductivity type, the drain drift region providing a vertical drift current path in the ON-state of the device and being depleted in the OFF-state of the device; and

a breakdown withstanding region around the drain drift region and between the first major surface and the layer of the first conductivity type, the breakdown withstanding region substantially not providing current path in the ON-state of the device and being depleted in the OFF-state of the device, the breakdown withstanding region comprising an alternating conductivity type layer comprising first regions of the first conductivity type and second regions of a second conductivity type, the first regions and the second regions being arranged alternately with each other.

2. The semiconductor device according to

claim 1

, wherein the drain drift region comprises an alternating conductivity type layer comprising vertical drift current path regions of the first conductivity type and vertical partition regions of the second conductivity type, the drift current path regions and the partition regions extending in the thickness direction of the semiconductor chip, and the drift current path regions and the partition regions being arranged alternately with each other.

3. The semiconductor device according to

claim 2

, wherein the alternating conductivity type layer in the breakdown withstanding region is doped more lightly than the alternating conductivity type layer in the drain drift region.

4. The semiconductor device according to

claim 2

, wherein the first regions and the second regions of the alternating conductivity type layer in the breakdown withstanding region extend in the thickness direction of the semiconductor chip, and the first regions and the second regions are contacting with each other.

5. The semiconductor device according to

claim 4

, wherein at least either the first regions or the second regions of the alternating conductivity type layer in the breakdown withstanding region comprise unit diffusion regions scattered in the thickness direction of the semiconductor chip and connected with each other.

6. The semiconductor device according to

claim 5

, the impurity concentration in each of the unit diffusion regions is the highest at the center thereof and decreases gradually toward the boundary thereof.

7. The semiconductor device according to

claim 2

, wherein the alternating conductivity type layer of the drain drift region comprises a laminate formed of a plurality of a pair of the drift current path region and the partition region and the alternating conductivity type layer of the breakdown withstanding region comprises a laminate formed of a plurality of a pair of the first region and the second region.

8. The semiconductor device according to

claim 2

, wherein the pitch of repeating in the breakdown withstanding region, at that the pair of the first region and the second region is repeated, is narrower than the pitch of repeating in the drain drift region, at that the pair of the drift current path region and the partition region is repeated.

9. The semiconductor device according to

claim 7

, wherein the pitch of repeating in the breakdown withstanding region, at that the pair of the first region and the second region is repeated, is narrower than the pitch of repeating in the drain drift region, at that the pair of the drift current path region and the partition region is repeated, and wherein the boundary planes between the first regions and the second regions of the breakdown withstanding region extend almost in parallel to the boundary planes between the drift current path regions and the partition regions of the drain drift region;

the plane, thereon the end faces of the first regions and the second regions are arranged alternately, is bonded to the plane, thereon the end faces of the drift current path region and the partition region are arranged alternately; and

the boundary plane of the innermost first region is bonded to the boundary plane of the outermost partition region.

10. The semiconductor device according to

claim 9

, wherein the drain drift region comprises a first transient region, therein the widths of the drift current path regions and the partition regions are decreasing gradually toward the breakdown withstanding region.

11. The semiconductor device according to

claim 9

, wherein the breakdown withstanding region comprises a second transient region, therein the widths of the first regions and the second regions are increasing gradually toward the drain drift region.

12. The semiconductor device according to

claim 10

, wherein the first transient region is below the edge portion of the first main electrode.

13. The semiconductor device according to

claim 11

, wherein the first transient region or the second transient region is below the edge portion of the first main electrode.

14. The semiconductor device according to

claim 7

, wherein the pitch of repeating in the breakdown withstanding region, at that the pair of the first region and the second region is repeated, is narrower than the pitch of repeating in the drain drift region, at that the pair of the drift current path region and the partition region is repeated, and wherein the boundaries between the first regions and the second regions of the breakdown withstanding region extend almost in perpendicular to the boundaries between the drift current path regions and the partition regions of the drain drift region.

15. The semiconductor device according to

claim 7

, wherein the pitch of repeating in the breakdown withstanding region, at that the pair of the first region and the second region is repeated, is narrower than the pitch of repeating in the drain drift region, at that the pair of the drift current path region and the partition region is repeated, and wherein the alternating conductivity type layer of the breakdown withstanding region comprises a first alternating conductivity type section including the first regions and the second regions, the boundary planes therebetween extend almost in parallel to the boundary planes between the drift current path regions and the partition regions of the drain drift region;

and a second alternating conductivity type section including the first regions and the second regions, the boundary planes therebetween extend in perpendicular to the boundary planes between the drift current path regions and the partition regions of the drain drift region.

16. The semiconductor device according to

claim 15

, wherein the plane, thereon the end faces of the first regions and the second regions of the first alternating conductivity type section are arranged alternately, is bonded to the plane, thereon the end faces of the drift current regions and the partition regions of the drain drift region are arranged alternately.

17. The semiconductor device according to

claim 16

, wherein the alternating conductivity type layer of the breakdown withstanding region further comprises a third alternating conductivity type section in the corner portion of the breakdown withstanding region defined by the first alternating conductivity type section and the second alternating conductivity type section;

the third alternating conductivity type section including the first regions and the second regions extending in parallel to the first regions and the second regions of the first alternating conductivity type section or the second alternating conductivity type section.

18. The semiconductor device according to

claim 15

, wherein the plane, thereon end faces of the first regions and the second regions of the first alternating conductivity type section or the second alternating conductivity type section are arranged alternately, is bonded to the boundary plane of the innermost second region of the second alternating conductivity type section or the first alternating conductivity type section.

19. The semiconductor device according to

claim 7

, the boundary planes between the first regions and the second regions of the breakdown withstanding region extend obliquely to the boundary planes between the drift current path regions and the partition regions of the drain drift region.

20. The semiconductor device according to

claim 7

, wherein the pn-junctions between the first regions and the second regions are almost flat.

21. The semiconductor device according to claims 7, wherein the pn-junctions between the first regions and the second regions are serpentine.

22. The semiconductor device according to

claim 2

, wherein at least either the first regions or the second regions of the alternating conductivity type layer in the breakdown withstanding region are columnar.

23. The semiconductor device according to

claim 2

, the semiconductor device further comprising a highly resistive region filling the space between the first regions and the second regions, and the highly resistive region being doped with an impurity of the first conductivity type and an impurity of the second conductivity type.

24. The semiconductor device according to

claim 2

, the semiconductor device further comprising one or more voltage equalizing rings of the second conductivity type on the first major surface, the one or more voltage equalizing rings surrounding the drain drift region, and the one or more voltage equalizing rings connecting the second regions of the second conductivity type.

25. The semiconductor device according to

claim 24

, wherein the impurity concentration in the one or more voltage equalizing rings is higher than the impurity concentration in the second region of the second conductivity type.

26. The semiconductor device according to

claim 2

, wherein at least either the first regions or the second regions of the alternating conductivity type layer in the breakdown withstanding region comprise unit diffusion regions scattered in the thickness direction of the semiconductor chip and spaced apart from each other.

27. The semiconductor device according to

claim 26

, wherein the impurity concentration in each unit diffusion region is the maximum at the center thereof and decreasing gradually toward the boundary of the unit diffusion region.

28. The semiconductor device according to

claim 1

, wherein the first regions and the second regions of the alternating conductivity type layer in the breakdown withstanding region extend almost in parallel or obliquely to the major surfaces of the semiconductor chip, and the first regions and the second regions are laminated alternately with each other.

31. The semiconductor device according to

claim 1

, the semiconductor device further comprising a surrounding region of the first conductivity type between the first major surface and the layer of the first conductivity type, the surrounding region surrounding the breakdown withstanding region, and the surrounding region exhibiting relatively low electrical resistance.

33. The semiconductor device according to

claim 31

, the semiconductor device further comprising a peripheral electrode on the surrounding region, the peripheral electrode being on the side of the first major surface.

35. The semiconductor device according to

claim 31

, the semiconductor device further comprising a channel stopper region of the first conductivity type on the surrounding region, and the channel stopper region being on the side of the first major surface.

37. The semiconductor device according to

claim 31

, wherein the drain drift region comprises an alternating conductivity type layer comprising vertical drift current path regions of the first conductivity type and vertical partition regions of the second conductivity type, the drift current path regions and the partition regions extending in the thickness direction of the semiconductor chip, the drift current path regions and the partition regions being arranged alternately with each other, and the width of the surrounding region is wider than the width of the drift current path region.

39. The semiconductor device according to

claim 31

, wherein the drain drift region comprises an alternating conductivity type layer comprising vertical drift current path regions of the first conductivity type and vertical partition regions of the second conductivity type, the drift current path regions and the partition regions extending in the thickness direction of the semiconductor chip, the drift current path regions and the partition regions being arranged alternately with each other, and the width of the surrounding region is wider than the spacing between the partition regions.

41. The semiconductor device according to

claim 1

, the semiconductor device further comprising an insulation film on the breakdown withstanding region, the insulation film being on the side of the first major surface.

29. A semiconductor device comprising:

a semiconductor chip having a first major surface and a second major surface opposing the first major surface;

an active region on a side of the first major surface;

a layer of a first conductivity type on a side of the second major surface, the layer of the first conductivity type exhibiting relatively low electrical resistance;

a first main electrode electrically connected to the active region;

a second main electrode electrically connected to the layer of the first conductivity type;

a drain drift region between the active region and the layer of the first conductivity type, the drain drift region providing a vertical drift current path in the ON-state of the device and being depleted in the OFF-state of the device; and

a breakdown withstanding region around the drain drift region and between the first major surface and the layer of the first conductivity type, the breakdown withstanding region substantially not providing a current path in the ON-state of the device and being depleted in the OFF-state of the device, the breakdown withstanding region comprising a highly resistive region doped with an impurity of the first conductivity type and an impurity of the second conductivity type.

30. The semiconductor device according to

claim 29

, wherein the drain drift region comprises an alternating conductivity type layer comprising vertical drift current path regions of the first conductivity type and vertical partition regions of the second conductivity type, the drift current path regions and the partition regions extending in the thickness direction of the semiconductor chip, and the drift current path regions and the partition regions being arranged alternately with each other.

32. The semiconductor device according to

claim 29

, the semiconductor device further comprising a surrounding region of the first conductivity type between the first major surface and the layer of the first conductivity type, the surrounding region surrounding the breakdown withstanding region, and the surrounding region exhibiting relatively low electrical resistance.

34. The semiconductor device according to

claim 32

, the semiconductor device further comprising a peripheral electrode on the surrounding region, the peripheral electrode being on the side of the first major surface.

36. The semiconductor device according to

claim 32

, the semiconductor device further comprising a channel stopper region of the first conductivity type on the surrounding region, and the channel stopper region being on the side of the first major surface.

38. The semiconductor device according to

claim 32

, wherein the drain drift region comprises an alternating conductivity type layer comprising vertical drift current path regions of the first conductivity type and vertical partition regions of the second conductivity type, the drift current path regions and the partition regions extending in the thickness direction of the semiconductor chip, the drift current path regions and the partition regions being arranged alternately with each other, and the width of the surrounding region is wider than the width of the drift current path region.

40. The semiconductor device according to

claim 32

, wherein the drain drift region comprises an alternating conductivity type layer comprising vertical drift current path regions of the first conductivity type and vertical partition regions of the second conductivity type, the drift current path regions and the partition regions extending in the thickness direction of the semiconductor chip, the drift current path regions and the partition regions being laminated alternately with each other, and the width of the surrounding region is wider than the spacing between the partition regions.

42. The semiconductor device according to

claim 29

, the semiconductor device further comprising an insulation film on the breakdown withstanding region, the insulation film being on the side of the first major surface.

43. A method of manufacturing a semiconductor device, the method comprising:

(a) growing a highly resistive first epitaxial layer on a semiconductor substrate, the semiconductor substrate exhibiting relatively low electrical resistance;

(b) selectively implanting an impurity of the first conductivity type into first portions of the first epitaxial layer and an impurity of a second conductivity type into second portions of the first epitaxial layer;

(c) growing a highly resistive second epitaxial layer on the first epitaxial layer;

(d) repeating the steps (b) and (c); and

(e) thermally driving the implanted impurities from the diffusion centers thereof, to form a first alternating conductivity type layer and a second alternating conductivity type layer.

44. The method according to

claim 43

, wherein the first portions and the second portions for forming the second alternating conductivity type layer in the breakdown withstanding region are narrower than the first portions and the second portions for forming the first alternating conductivity type layer in a drain drift region.

45. The method according to

claim 44

, wherein the pitch of repeating, thereat a pair of the first portion and the second portion is repeated for forming the second alternating conductivity type layer in a breakdown withstanding region, is narrower than the pitch of repeating, thereat a pair of the first portion and the second portion is repeated for forming a first alternating conductivity type layer in the drain drift region.

46. A method of manufacturing a semiconductor device, the method comprising:

(a) growing a highly resistive first epitaxial layer on a semiconductor substrate with low electrical resistance, the semiconductor substrate including a layer of first conductivity type;

(b) implanting an impurity of the first conductivity type or a second conductivity type into substantially the entire surface portion of the first epitaxial layer and selectively implanting an impurity of the first conductivity type or the second conductivity type into selected surface portions of the first epitaxial layer;

(c) growing a highly resistive second epitaxial layer on the first epitaxial layer;

(d) repeating the steps (b) and (c); and

(e) thermally driving the implanted impurities to form a first alternating conductivity type layer and a second alternating conductivity type layer.

47. The method according to

claim 46

, wherein the selected surface portions of the second alternating conductivity type layer in the breakdown withstanding region are narrower than the selected surface portions of the first alternating conductivity type layer in a drain drift region, and the pitch of repeating, thereat the selected surface portions are repeated for forming the second alternating conductivity type layer in a breakdown withstanding region, is narrower than the pitch of repeating, thereat the selected surface portions are repeated for forming the first alternating conductivity type layer in the drain drift region.