Semiconductor device including memory unit and semiconductor module including memory units

• US 20010028114A1
• Filed: 03/26/2001
• Published: 10/11/2001
• Est. Priority Date: 03/27/2000
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hosomi, Eiichi
• Granted Patent: US 6,740,981 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA

Abstract

A semiconductor device comprises a memory unit, a selecting signal terminal, and an identifying unit. The selecting signal terminal receives a memory unit selecting signal which is commonly transmitted to a plurality of memory units. The identifying unit distinguishes the memory unit from other memory units on the basis of the memory unit selecting signal, and includes an identifier generating circuit and a memory unit selecting circuit. A plurality of semiconductor devices are laid one over after another, thereby constituting a semiconductor module.

Claims

1. A semiconductor device comprising:

a memory unit;

a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and

an identifying unit which includes at least a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned to the memory unit and the memory unit selecting signal, and an identifier generating circuit for generating identifiers for other memory units on the basis of the identifier.

2. The semiconductor device of

claim 1

, wherein the identifier generating circuit is mainly constituted by an adder circuit or a subtracter circuit.

3. The semiconductor device of

claim 1

, wherein the identifier is one bit data or a plurality of bit data, and the identifier generating circuit is an adder circuit for carrying the identifier data of the memory unit bit by bit.

4. The semiconductor device of

claim 3

, wherein the identifier generating circuit is the adder circuit for carrying the identifier of the memory unit by a half bit.

5. The semiconductor device of

claim 1

, wherein the identifier generating circuit is electrically connected to a standard voltage power supply for a circuit system or a circuit operation power supply, and the standard voltage power supply voltage or the circuit operation power supply is used as the identifier.

6. The semiconductor device of

claim 1

, wherein the memory unit selecting circuit is a comparator for compares the identifier with the memory unit selecting signal.

7. The semiconductor device of

claim 1

, wherein the memory unit is either a DRAM or an SRAM.

8. The semiconductor device of

claim 1

, wherein the memory unit is a non-volatile memory which is ROM, EPROM or EEPROM.

9. The semiconductor device of

claim 1

, wherein the selecting signal terminal which receives the memory unit selecting signal is a surplus signal terminal out of address signal terminals which are used for selecting address of the memory unit.

10. A semiconductor device comprising:

a memory unit;

a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and

an identifying unit which is provided outside the memory unit and includes at least a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned thereto and a memory unit selecting signal, and an identifier generating circuit for generating identifiers for other memory units on the basis of the identifier of the memory unit.

11. The semiconductor device of

claim 10

, wherein the memory unit and the identifying unit are constituted by separate semiconductor chips.

12. The semiconductor device of

claim 11

, wherein the semiconductor chips constituting the memory unit and the identifying unit are constituted by separate packages.

13. The semiconductor device of

claim 11

, wherein the semiconductor chips constituting the memory unit and the identifying unit are constituted by the same package.

14. The semiconductor device of

claim 11

, wherein the selecting signal terminal is provided in the semiconductor chip constituting the identifying unit.

15. A semiconductor module comprising:

a first memory unit;

a second memory unit positioned on or by the first memory unit;

a first selecting signal terminal provided in the first memory unit and for receiving a memory unit selecting signal which is common to a plurality of memory units;

a second selecting signal terminal provided in the second memory unit and for receiving the memory unit selecting signal which is common to a plurality of memory units;

a first identifying unit including at least;

a first memory unit selecting circuit for selecting the first memory unit on the basis of a first identifier assigned thereto and the memory unit selection signal; and

a first identifier generating circuit for generating a second identifier for the second memory unit on the basis of the first identifier; and

a second identifying unit including at least;

a second memory unit selecting circuit for selecting the second memory unit on the basis of the second identifier assigned thereto and the memory unit selection signal; and

a second identifier generating circuit for generating a third identifier for a third memory unit on the basis of the second identifier.

16. The semiconductor module of

claim 15

, wherein the first and second identifier generating circuits are mainly constituted by adder or subtracter circuits.

17. The semiconductor module of

claim 15

, wherein the first identifier generating circuit is electrically connected to a standard voltage power supply for a circuit system or a circuit operation power supply, and the standard voltage power supply or the circuit operation power supply is used as the first identifier.

18. The semiconductor module of

claim 15

, wherein the first memory unit selecting circuit is a comparator for compares the first identifier and the memory unit selecting signal, and the second memory unit selecting circuit is a comparator for compares the second identifier and the memory unit selecting signal.

19. The semiconductor module of

claim 15

, wherein the second memory unit is stacked on the first memory unit.

20. The semiconductor module of

claim 15

, wherein the second memory unit is juxtaposed to the first memory unit.

21. The semiconductor module of

claim 15

further comprising at least one memory unit and at least one identifying unit.

22. A semiconductor device comprising:

a memory unit;

a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and

an identifying unit at least including an identifier generating circuit provided with at least a fuse element for generating an identifier assigned to the memory unit, and a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned thereto and the memory unit selecting signal.

23. The semiconductor device of

claim 22

, wherein:

the identifier generating circuit further includes a resistance element;

the fuse element has one end thereof electrically connected to a standard voltage power supply for a circuit system and the other end thereof electrically connected to the memory unit selecting circuit and one end of the resistance element; and

the resistance element has the other end thereof electrically connected to the circuit operation power supply for the circuit system.

24. The semiconductor device of

claim 23

, wherein the resistor element has a resistance value which is higher than a resistance value of the fuse element.

25. A semiconductor device comprising:

a memory unit;

a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and

an identifying unit at least including an identifier generating circuit provided with at least a wire for generating an identifier for the memory unit, and a memory unit selecting circuit for selecting the memory unit on the basis of the identifier assigned thereto and the memory unit selecting signal.

26. The semiconductor device of

claim 25

, wherein the wire has one end thereof electrically connected to a standard voltage power supply for a circuit system or a circuit operation power supply for a circuit system and the other end thereof electrically connected to the memory unit selecting circuit.