Semiconductor memory device having replacing defective columns with redundant columns

• US 20010028584A1
• Filed: 03/27/2001
• Published: 10/11/2001
• Est. Priority Date: 03/28/2000
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakayama, Atsushi, Haga, Ryo
• Granted Patent: US 6,459,630 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

A semiconductor memory device comprises a data line shifting circuit for connecting a plurality of data lines and spare data lines to a plurality of I/O data lines, a plurality of I/O numbering circuits for assigning the I/O data lines shift indicating numbers as locational information, the shift indicating numbers incrementing by one for each start point for data line shifting executed by the data line shifting circuit, a selection circuit for storing the correlationship between defective column addresses and the shift indicating numbers and outputting a selection signal corresponding to the shift indicating numbers when a defective-column address is input, a shift control circuit for comparing the selection signal with the shift indicating numbers and outputting a shift control signal to the data line shifting circuit based on a result of the comparison, and a number setting selecting circuit for selectively using a plurality of I/O numbering circuits.

Claims

1. A semiconductor memory device comprising:

a memory cell array including memory cells arranged in a matrix and having a plurality of columns;

at least one redundant column cell array provided adjacent to said memory cell array, for relieving defective columns in said memory cell array;

a plurality of data lines for transferring readout data read out from said memory cell array or write data to be written to said memory cell array;

at least one spare data line provided adjacent to the plurality of data lines, for transferring readout data read out from said redundant column cell array or write data to be written to said redundant column cell array;

a plurality of I/O lines provided correspondingly to said plurality of data lines, for transmitting and receiving readout/write data to and from said plurality of data lines;

a data line-shifting circuit for receiving a shift control signal and controlling connections between said plurality of I/O lines and both said plurality of data lines and said at least one spare data line based on said shift control signal;

a first I/O number generating circuit for generating, as locational information assigned to each of said plurality of I/O lines, shift indicating numbers that increment by one for each of a plurality of I/O lines starting with said I/O line corresponding to said data line to transfer data on a defective one of said plurality of columns, the plurality of I/O lines including said I/O line and arranged on one side relative to said I/O line;

a second I/O number generating circuit for generating shift indicating numbers all having the same value, as locational information assigned to each of said plurality of I/O lines;

a shift indicating number selecting circuit for selecting shift indicating numbers generated by said first and second I/O number generating circuits;

a shift indicating number memory circuit for storing said shift indicating numbers selected by said shift indicating number selecting circuit;

a selection circuit for storing a correlationship between addresses of said defective columns and said shift indicating numbers and outputting a selection signal corresponding to said shift indicating numbers when said address of said defective column is input; and

a shift control circuit for receiving inputs of said selection signal output from said selection circuit and said shift indicating signal stored in said shift indicating number memory circuit and comparing said selection signal and said shift indicating number together to output said shift control signal to said data line-shifting circuit based on a result of said comparison,

wherein if said shift indicating number selecting circuit selects the shift indicating number generated by said first I/O number generating circuit, said data line shifting circuit receives the shift control signal output from said shift control circuit and performs a first connection control operation of excluding said data line to transfer data on said defective column to sequentially shift a plurality of data lines adjacent to the excluded data line on one side thereof before correspondingly connecting the shifted data lines and said at least one spare data line to said plurality of I/O lines.

2. The semiconductor memory device according to

claim 1

, wherein when said shift control signal is output from said shift control circuit to said data line shifting circuit based on the result of the comparison with said selection signal, said second I/O number generating circuit generates a shift indicating number corresponding to a forced disable mode for disabling said first connection control operation by said data line shifting circuit.

3. The semiconductor memory device according to

claim 1

, wherein when said shift control signal is output from said shift control circuit to said data line shifting circuit based on the result of the comparison with said selection signal, said second I/O number generating circuit generates a shift indicating number corresponding to a forced access mode for causing said data line shifting circuit to sequentially shift all of said plurality of data lines before correspondingly connecting the shifted data line and said at least one spare data line to said plurality of I/O lines.

4. The semiconductor memory device according to

claim 1

, wherein said shift indicating number selecting circuit selects said shift indicating number generated by said second I/O number generating circuit without destroying said shift indicating number generated by said first I/O number generating circuit.

5. The semiconductor memory device according to

claim 4

, wherein said first I/O number generating circuit includes a data serial transferring circuit.

6. A semiconductor memory device comprising:

a memory cell array including memory cells arranged in a matrix and having a plurality of columns;

at least one redundant column cell array provided adjacent to said memory cell array, for relieving defective columns in said memory cell array;

a plurality of data lines for transferring readout data read out from said memory cell array or write data to be written to said memory cell array;

at least one spare data line provided adjacent to said plurality of data lines, for transferring readout data read out from said redundant column cell array or write data to be written to said redundant column cell array;

a plurality of I/O lines provided correspondingly to said plurality of data lines, for transmitting and receiving readout/write data to and from said plurality of data lines;

a data line shifting circuit for receiving a shift control signal and controlling connections between said plurality of I/O lines and both said plurality of data lines and said at least one spare data line based on the shift control signal;

an I/O number generating circuit for generating, as locational information assigned to each of said plurality of I/O lines, shift indicating numbers that increment by one for each of a plurality of I/O line starting with said I/O line corresponding to said data line to transfer data on a defective one of said plurality of columns, the plurality of I/O lines including said I/O line and arranged on one side relative to said I/O line;

a shift indicating number modifying circuit for modifying all said shift indicating numbers generated by said I/O number generating circuit so as to have the same value;

a selection circuit for storing a correlationship between addresses of said defective columns and said shift indicating numbers and outputting a selection signal corresponding to said shift indicating numbers when said address of said defective column is input; and

a shift control circuit for receiving inputs of said selection signal output from said selection circuit and said shift indicating signal stored in said shift indicating number memory circuit and comparing said selection signal and said shift indicating number together to output said shift control signal to said data line shifting circuit based on a result of said comparison, wherein if said shift indicating number modifying circuit does not modify said shift indicating number, said data line shifting circuit receives the shift control signal output from said shift control circuit and performs a first connection control operation of excluding said data line to transfer data on said defective column to sequentially shift a plurality of data lines adjacent to said excluded data line on one side thereof before correspondingly connecting the shifted data lines and said at least one spare data line to said plurality of I/O lines.

7. A semiconductor memory device according to

claim 6

, wherein said shift indicating number modifying circuit modifies all said shift indicating numbers so as to have the same value, according to a forced disable mode for disabling said first connection control operation by said data line shifting circuit.

8. A semiconductor memory device according to

claim 6

, wherein said shift indicating number modifying circuit modifies all said shift indicating numbers so as to have the same value, according to a forced access mode for causing said data line shifting circuit to sequentially shift all of said plurality of data lines before correspondingly connecting the shifted data line and said at least one spare data line to said plurality of I/O lines.

9. A semiconductor memory device according to

claim 6

, wherein said I/O number generating circuit includes:

a memory circuit in which data to be stored are programmed;

a transfer circuit for transferring the data programmed in said memory circuit; and

a comparison circuit for comparing the data transferred from said transfer circuit with other data, wherein said shift indicating number modifying circuit modifies the data transferred by said transfer circuit.

10. A semiconductor memory device comprising:

a memory cell array including normal memory cells and redundancy memory cells;

a comparison circuit for comparing information input for addressing the memory cell array with information identifying a defective portion of the memory cell array;

a first number generating circuit for assigning different numbers to a plurality of select lines which are used for selecting the normal memory cell and the redundancy memory cells in units of a predetermined number of cells;

at least one second number generating circuit for assigning numbers, which are different from the numbers assigned by the first number generating circuit, to the select lines; and

a driving circuit for driving the select lines based on the numbers assigned by the first or second number generating circuits and a comparison result output from the comparison circuit.

11. A semiconductor memory device comprising:

a memory cell array including normal memory cells and redundancy memory cells;

a plurality of word lines connected to the normal memory cells;

a plurality of redundancy word lines connected to the redundancy memory cells;

a comparison circuit for comparing information input for selecting the word lines with information identifying a defective word line which, if any, is included among the word lines;

a first number generating circuit for assigning different numbers to the word lines and the redundancy word lines;

at least one second number generating circuit for assigning numbers, which are different from the numbers assigned by the first number generating circuit, to the word lines and redundancy word lines; and

a driving circuit for driving the word lines and redundancy word lines based on the numbers assigned by the first or second number generating circuits and a comparison result output from the comparison circuit.

12. A semiconductor memory device comprising:

a memory cell array including normal memory cells and redundancy memory cells;

a plurality of bit lines connected to the normal memory cells;

a plurality of redundancy bit lines connected to the redundancy memory cells;

a comparison circuit for comparing information input for selecting the bit lines with information identifying a defective bit line which, if any, is included among the bit lines;

a first number generating circuit for assigning different numbers to the bit lines and the redundancy bit lines;

at least one second number generating circuit for assigning numbers, which are different from the numbers assigned by the first number generating circuit, to the bit lines and redundancy bit lines; and

a selecting circuit for selecting the bit lines and redundancy bit lines based on the numbers assigned by the first or second number generating circuits and a comparison result output from the comparison circuit.