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Semiconductor memory device having replacing defective columns with redundant columns

  • US 20010028584A1
  • Filed: 03/27/2001
  • Published: 10/11/2001
  • Est. Priority Date: 03/28/2000
  • Status: Active Grant
First Claim
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1. A semiconductor memory device comprising:

  • a memory cell array including memory cells arranged in a matrix and having a plurality of columns;

    at least one redundant column cell array provided adjacent to said memory cell array, for relieving defective columns in said memory cell array;

    a plurality of data lines for transferring readout data read out from said memory cell array or write data to be written to said memory cell array;

    at least one spare data line provided adjacent to the plurality of data lines, for transferring readout data read out from said redundant column cell array or write data to be written to said redundant column cell array;

    a plurality of I/O lines provided correspondingly to said plurality of data lines, for transmitting and receiving readout/write data to and from said plurality of data lines;

    a data line-shifting circuit for receiving a shift control signal and controlling connections between said plurality of I/O lines and both said plurality of data lines and said at least one spare data line based on said shift control signal;

    a first I/O number generating circuit for generating, as locational information assigned to each of said plurality of I/O lines, shift indicating numbers that increment by one for each of a plurality of I/O lines starting with said I/O line corresponding to said data line to transfer data on a defective one of said plurality of columns, the plurality of I/O lines including said I/O line and arranged on one side relative to said I/O line;

    a second I/O number generating circuit for generating shift indicating numbers all having the same value, as locational information assigned to each of said plurality of I/O lines;

    a shift indicating number selecting circuit for selecting shift indicating numbers generated by said first and second I/O number generating circuits;

    a shift indicating number memory circuit for storing said shift indicating numbers selected by said shift indicating number selecting circuit;

    a selection circuit for storing a correlationship between addresses of said defective columns and said shift indicating numbers and outputting a selection signal corresponding to said shift indicating numbers when said address of said defective column is input; and

    a shift control circuit for receiving inputs of said selection signal output from said selection circuit and said shift indicating signal stored in said shift indicating number memory circuit and comparing said selection signal and said shift indicating number together to output said shift control signal to said data line-shifting circuit based on a result of said comparison, wherein if said shift indicating number selecting circuit selects the shift indicating number generated by said first I/O number generating circuit, said data line shifting circuit receives the shift control signal output from said shift control circuit and performs a first connection control operation of excluding said data line to transfer data on said defective column to sequentially shift a plurality of data lines adjacent to the excluded data line on one side thereof before correspondingly connecting the shifted data lines and said at least one spare data line to said plurality of I/O lines.

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