High frequency circuit using high output amplifier cell block and low output amplifier cell block

• US 20010029168A1
• Filed: 04/05/2001
• Published: 10/11/2001
• Est. Priority Date: 04/05/2000
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamaguchi, Keiichi
• Granted Patent: US 6,804,500 B2
• Time in Patent Office: Days
• US Class Current: 455/73
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1423 Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H03F 1/0283 : Reducing the number of DC-current paths
• CPC Class Codes: H03F 2203/7236 : the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

A high frequency circuit capable of realizing a power amplifier with a wide dynamic range in which it is hard to degrade the power addition efficiency at low output is formed by using a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals, and a low output amplifier cell block configured to amplify input signals at a time of low output power, in which a DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to input/output signals.

Claims

1. A high frequency circuit, comprising:

a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals;

a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals;

a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and

a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted.

2. The high frequency circuit of

claim 1

, wherein the high output amplifier cell block and the low output amplifier cell block are controlled by control voltages to put either one of the high output amplifier cell block and the low output amplifier cell block in an amplification operation state and another one of the high output amplifier cell block and the low output amplifier cell block in a high impedance state.

3. The high frequency circuit of

claim 2

, wherein the first and second connection units are formed by passive elements alone and configured to maintain a matching state with respect to the low output amplifier cell block when the high output amplifier cell block is in the high impedance state or a matching state with respect to the high output amplifier cell block when the low output amplifier cell block is in the high impedance state.

4. The high frequency circuit of

claim 1

, further comprising:

at least one middle output amplifier cell block configured to amplify the input signals at a time of middle output power, in which the DC power source voltage is supplied in parallel to third amplifier cells and in series to fourth amplifier cells that are connected in parallel AC-wise with respect to the input/output signals.

5. The high frequency circuit of

claim 1

, wherein the DC power source voltage is supplied from an output port side of the second connection unit.

6. The high frequency circuit of

claim 1

, wherein a common control voltage for controlling the high output amplifier cell block and the low output amplifier cell block is supplied from an input port side of the first connection unit.

7. The high frequency circuit of

claim 1

, wherein the high output amplifier cell block and the low output amplifier cell block are mounted on separate semiconductor chips.

8. The high frequency circuit of

claim 1

, wherein the high output amplifier cell block and the low output amplifier cell block are mounted on a single semiconductor chip.

9. The high frequency circuit of

claim 8

, wherein the first amplifier cells and the second amplifier cells are arranged in a distributed pattern over the single semiconductor chip.

10. The high frequency circuit of

claim 1

, wherein source and load impedances of each of the high output amplifier cell block and the low output amplifier cell block are fine tuned by forming the first and second connection units asymmetrically with respect to the high output amplifier cell block and the low output amplifier cell block.

11. The high frequency circuit of

claim 1

, wherein source and load impedances of each of the high output amplifier cell block and the low output amplifier cell block are fine tuned by using different transistor sizes for the high output amplifier cell block and the low output amplifier cell block.

12. The high frequency circuit of

claim 1

, wherein source and load impedances of each of the high output amplifier cell block and the low output amplifier cell block are fine tuned by arranging the first amplifier cells and the second amplifier cells at different distances from matching circuits to be connected at an input side of the first connection unit and an output side of the second connection unit.

13. A communication device, comprising:

at least one antenna configured to transmit or receive radio signals;

at least one power amplifier configured to amplify the radio signals to be transmitted or received by the at least one antenna, including a high frequency circuit formed by;

a high output amplifier cell block configured to amplify input signals at a time of high output power, in