Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements

• US 20010029515A1
• Filed: 02/26/2001
• Published: 10/11/2001
• Est. Priority Date: 05/08/1998
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Mirsky, Ethan A.
• Granted Patent: US 6,591,357 B2
• Time in Patent Office: Days
• US Class Current: 708/232
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/505 in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence

Abstract

A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The saturation signal is generated using logic that tests for saturation in the data path. The ALUs of the data path are further coupled using a right-going carry chain for transmitting the saturation signal back down the data path. The saturation signal is transmitted from the MSB ALU through the ALUs of the data path to the LSB ALU using a first back propagation channel. A signal that selects a saturation value is transmitted from the MSB ALU to the LSB ALU using a second back propagation channel. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to the saturation signal. The carry chains support carry operations for non-local functions comprising minimum and maximum arithmetic functions.

Claims

1. A method for using a data path comprising a plurality of processing elements (PEs), the method comprising the steps of:

transmitting at least one carry bit from a first PE to a second PE using a left-going carry chain;

generating at least one signal in the second PE in response to the received carry bit; and

transmitting the at least one signal from the second PE to the first PE using a right-going carry chain, wherein the at least one signal reconfigures the data path.

2. The method of

claim 1

, wherein the first PE comprises a least significant byte of the data path and the second PE comprises a most significant byte of the data path.

3. The method of

claim 1

, wherein the step of transmitting at least one signal from the second PE to the first PE comprises transmitting the at least one signal through each PE of the data path, wherein each PE uses logic to manipulate a resident bit sequence in response to the at least one signal.

4. The method of

claim 3

, wherein the logic is configurable.

5. The method of

claim 1

, further comprising the steps of:

transmitting configuration data to the plurality of PEs;

defining the data path by designating the plurality of PEs in response to the configuration data; and

programming the plurality of PEs that comprise the data path in response to the configuration data.

6. The method of

claim 5

, further comprising the steps of:

setting a flag in the first PE in response to the configuration data, the flag designating the first PE as comprising the least significant byte of the data path; and

and setting a flag in the second PE in response to the configuration data, the flag designating the second PE as comprising the most significant byte of the data path.

7. The method of

claim 1

, wherein the step of generating at least one signal comprises the step of using logic to test for saturation in the data path.

8. The method of

claim 1

, wherein the left- and right-going carry chains support carry operations for non-local functions comprising saturated and minimum and maximum arithmetic functions.

9. The method of

claim 8

, wherein each PE of the data path is programmed to support the same function, the programming occurring through at least one function port of each PE.

10. The method of

claim 1

, wherein the left-going carry chain comprises at least one forward channel between the first and the second PEs.

11. The method of

claim 1

, wherein the right-going carry chain comprises at least one back propagation channel between the second and the first PEs, the at least one back propagation channel coupling the plurality of PEs of the data path.

12. The method of

claim 11

, wherein a saturation signal is transmitted over a first back propagation channel.

13. The method of

claim 11

, wherein a signal that selects a saturation value is transmitted over a second back propagation channel.

14. The method of

claim 1

, wherein the plurality of processing elements comprises a plurality of multiple context processing elements.

15. An apparatus for using a data path comprising a plurality of processing elements (PEs), the apparatus comprising:

a left-going carry chain for transmitting at least one carry bit from a first PE to a second PE;

logic for generating at least one signal in the second PE in response to the received carry bit; and

a right-going carry chain for transmitting the at least one signal from the second PE to the first PE, wherein the at least one signal reconfigures the data path.

16. The apparatus of

claim 15

, wherein the first PE comprises a least significant byte of the data path and the second PE comprises a most significant byte of the data path, and wherein the at least one signal is transmitted from the second PE to the first PE by passing through each PE of the data path, wherein each PE uses logic to manipulate a resident bit sequence in response to the at least one signal.

17. The apparatus of

claim 16

, wherein the logic is configurable.

18. The apparatus of

claim 15

, further comprising:

a controller for transmitting configuration data to the plurality of PEs;

logic for defining the data path by designating the plurality of PEs in response to the configuration data; and

logic for programming the plurality of PEs that comprise the data path in response to the configuration data.

19. The apparatus of

claim 15

, wherein the at least one signal generated in the second PE is generated using logic, the logic testing for saturation in the data path.

20. The apparatus of

claim 15

, wherein the right-going carry chain comprises at least one back propagation channel between the second and the first PEs, the at least one back propagation channel coupling the plurality of PEs of the data path.

21. The apparatus of

claim 15

, wherein the plurality of processing elements comprises a plurality of multiple context processing elements (MCPEs).

22. The apparatus of

claim 21

, further comprising at least one configuration memory context in each of the plurality of MCPEs, the at least one configuration memory context controlling each of the plurality of MCPEs in response to the configuration data.

25. The system of

claim 21

, wherein the logic is configurable.

23. A system for using a data path in a reconfigurable computing device, the system comprising:

an array of processing elements (PEs);

a network coupled to the array of PEs, the network transmitting configuration data;

a left-going carry chain for transmitting at least one carry bit from a first PE to a second PE; and

a right-going carry chain for transmitting at least one signal from the second PE to the first PE, wherein the at least one signal reconfigures the data path.

24. The system of

claim 23

, further comprising logic for generating at least one signal in the second PE in response to the received carry bit.

26. The system of

claim 23

, wherein the first PE comprises a least significant byte of the data path and the second PE comprises a most significant byte of the data path.

27. The system of

claim 23

, wherein the at least one signal is transmitted from the second PE to the first PE by passing through each PE of the data path, wherein each PE uses logic to manipulate a resident bit sequence in response to the at least one signal.

28. The system of

claim 23

, wherein the network comprises:

a transmitter for transmitting configuration data to the plurality of PEs;

logic for defining the data path by designating the plurality of PEs in response to the configuration data; and

logic for programming the plurality of PEs that comprise the data path in response to the configuration data.

29. The system of

claim 23

, wherein the at least one signal generated in the second PE is generated using logic to test for saturation in the data path.

30. The system of

claim 23

, wherein each PE of the data path is programmed to support non-local functions comprising saturated and minimum and maximum arithmetic functions, the programming occurring through at least one function port of each PE.

31. The system of

claim 23

, wherein the left-going carry chain comprises at least one forward channel between the first and the second PEs, and wherein the right-going carry chain comprises at least one back propagation channel between the second and the first PEs, the at least one back propagation channel coupling the plurality of PEs of the data path.

32. The apparatus of

claim 23

, wherein the plurality of processing elements comprises a plurality of multiple context processing elements (MCPEs).

33. The system of

claim 32

, wherein each of the plurality of MCPEs comprises at least one configuration memory context.