Semiconductor device analyzer, method for analyzing/manufacturing semiconductor device, and storage medium storing program for analyzing semiconductor device

• US 20010029601A1
• Filed: 03/26/2001
• Published: 10/11/2001
• Est. Priority Date: 03/27/2000
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kimura, Tomohisa, Okumura, Makiko
• Granted Patent: US 7,016,820 B2
• Time in Patent Office: Days
• US Class Current: 716/19
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A semiconductor device analyzer has a substrate model reading module, a Y-matrix entry module, a discriminating module, a matrix reduction module, and an output format discriminating module. The substrate model reading module reads a substrate network model of three-dimensional meshes representing the substrate of a semiconductor device. The substrate network model is a network of resistive and capacitive elements and is used for the simulation and analysis of the semiconductor substrate. The Y-matrix entry module prepares a Y-matrix from the substrate network model, each element of the Y-matrix being expressed with a polynomial of differential operator “s”. The discriminating module discriminates internal nodes to be eliminated from external nodes to be left among the nodes of the substrate network model. The matrix reduction module eliminates the internal nodes, thereby reducing the Y-matrix. The output format determining module determines an output format for an operation result.

Claims

1. A semiconductor device analyzer comprising:

a substrate model reading module configured to read, from input data to the semiconductor device analyzer, a substrate network model of three-dimensional meshes representing a substrate of a semiconductor device at a surface of and in which circuit elements are merged;

a Y-matrix entry module configured to prepare a Y-matrix from the substrate network model and express each element of the Y-matrix with a polynomial of differential operator “

s”

;

a discriminating module configured to discriminate internal nodes to be eliminated from and external nodes to be left in the substrate network model; and

a matrix reduction module configured to reduce the Y-matrix by eliminating the internal nodes.

2. The analyzer of

claim 1

, further comprising an input unit configured to set an upper limit on the degree of the polynomial of differential operator “

s”

.

3. The analyzer of

claim 1

, further comprising an output format determining module configured to determine an output format for an operation result provided by the matrix reduction module.

4. A method for analyzing semiconductor device, comprising:

discriminating, among data prescribed in an input format for a circuit simulator, data expressing a substrate network model of three-dimensional meshes representing a substrate of the semiconductor device at a surface of and in which circuit elements are merged;

reading the data expressing the substrate network model;

preparing a Y-matrix from the data expressing the substrate network model;

expressing each element of the Y-matrix with a polynomial of differential operator “

s”

;

discriminating elements of the Y-matrix corresponding to internal nodes to be eliminated from and external nodes to be left in the substrate network model; and

reducing the Y-matrix by eliminating the internal nodes.

5. The method of

claim 4

, further comprising externally setting an upper limit on the degree of the polynomial of differential operator “

s”

.

6. The method of

claim 4

, further comprising determining whether or not the dimension of the reduced Y-matrix is equal to the number of the external nodes and iterating, until the dimension of the reduced Y-matrix becomes equal to the number of the external nodes, a sequence including the reading step, Y-matrix preparing step, polynomial expressing step, discriminating step, and Y-matrix reducing step.

7. The method of

claim 4

, further comprising leaving the reduced Y-matrix whose dimension is equal to the number of the external nodes as it is so as to provide stamps.

8. The method of

claim 4

, further comprising determining an output format for the reduced Y-matrix.

9. The method of

claim 8

, wherein the output format is one of a resistive network reconstituted from the reduced Y-matrix, an RC network reconstituted from the reduced Y-matrix, a circuit matrix based on the reduced Y-matrix and representing a multi-port network, and an RC or RCL network of filter circuits based on the reduced Y-matrix.

10. The method of

claim 4

, further comprising reconstituting data in the input format for the circuit simulator from the reduced Y-matrix.

11. The method of

claim 4

, wherein the substrate network model is made of an RC network.

12. A method for manufacturing a semiconductor device comprising:

discriminating, among data prescribed in an input format for a circuit simulator, data expressing a substrate network model of three-dimensional meshes representing a substrate of the semiconductor device at a surface of and in which circuit elements are merged;

reading the data expressing the substrate network model;

preparing a Y-matrix from the data expressing the substrate network model;

expressing each element of the Y-matrix with a polynomial of differential operator “

s”

;

discriminating elements of the Y-matrix corresponding to internal nodes to be eliminated from and external nodes to be left in the substrate network model;

reducing the Y-matrix by eliminating the internal nodes;

reconstituting data in the input format for the circuit simulator from the reduced Y-matrix; and

carrying out a circuit simulation with the reconstituted data for the circuit simulator, to analyze the influence of parasitic elements in the substrate on wiring capacitance of the semiconductor device.

13. The method of

claim 12

, further comprising:

carrying out a process simulation based on required design specifications, to provide doping profiles in the substrate; and

carrying out a device simulation according to the doping profiles provided by the process simulation and given electric boundary conditions so that the data in the circuit simulator input format is provided as the output data of the device simulation.

14. The method of

claim 13

, wherein the device simulation provides device behavior of the semiconductor device as an input data for the circuit simulation.

15. The method of

claim 12

, further comprising determining whether or not a result of the circuit simulation satisfies required circuit performances.

16. The method of

claim 15

, further comprising designing, if the result of the circuit simulation satisfies the required circuit performances, mask patterns based on the data provided by the process simulation, device simulation, and circuit simulation and fabricating a set of masks.

17. The method of

claim 16

, further comprising carrying out a wafer process with use of the set of masks.

18. A computer program product for controlling a semiconductor device analyzer, the program product comprising:

a storage medium readable by the semiconductor device analyzer;

and

a program recorded on the storage medium configured to be executed on the semiconductor device analyzer, the program comprising;

discriminating, among data prescribed in an input format for a circuit simulator, data expressing a substrate network model of three-dimensional meshes representing a substrate of the semiconductor device at a surface of and in which circuit elements are merged;

reading the data expressing the substrate network model;

preparing a Y-matrix from the data expressing the substrate network model;

expressing each element of the Y-matrix with a polynomial of differential operator “

s”

;

discriminating elements of the Y-matrix corresponding to internal nodes to be eliminated from and external nodes to be left in the substrate network model; and

reducing the Y-matrix by eliminating the internal nodes.

19. The computer program product of

claim 18

, wherein the program further comprises determining whether or not the dimension of the reduced Y-matrix is equal to the number of the external nodes and iterating, until the dimension of the reduced Y-matrix becomes equal to the number of the external nodes, a sequence including the reading, Y-matrix forming, polynomial expressing, discriminating, and Y-matrix reducing.

20. The computer program product of

claim 18

, wherein the program further comprises leaving the reduced Y-matrix whose dimension is equal to the number of the external nodes as it is so as to provide stamps.