Encoding device mounted on one chip for multiplexing video signal and audio signal

• US 20010031008A1
• Filed: 03/22/2001
• Published: 10/18/2001
• Est. Priority Date: 04/17/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Segawa, Hiroshi, Kumaki, Satoshi
• Granted Patent: US 6,765,961 B2
• Time in Patent Office: Days
• US Class Current: 375/240.26
• CPC Class Codes: H04N 21/2368 Multiplexing of audio and video streams
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams

Abstract

An encoding device includes a processor unit controlling an overall operation and at the same time having a software for executing an audio encoding process, a video encoding unit to execute a video encoding process, a multiplex process unit to execute a system process and a timing control unit to generate a timing signal for activating an audio encoding process, a video encoding process and a system process, all of these elements are mountable on the same substrate. Each of a control process for controlling the audio encoding process, the video encoding process and system process is executed as an interrupt process. The processor unit includes an interrupt control circuit. The interrupt control circuit selects, based on a predetermined priority, one interrupt process corresponding to at least one generated timing signal.

Claims

1. An encoding device multiplexing an input video signal and an input audio signal according to a predetermined compression encoding standard, comprising:

a processor unit having a function of executing an audio encoding process to convert said audio signal to encoded audio data, a function of executing a first control process for controlling a video encoding process and a function of executing a second control process for controlling a system process;

a timing control unit to generate at least one first timing signal for activating said video encoding process, a second timing signal for activating said audio encoding process and a third timing signal for activating said system process;

a first buffer to hold said encoded audio data temporarily;

a video encoding process unit, activated in response to said first timing signal, to execute said video encoding process for converting said video signal to encoded video data;

a second buffer to hold said encoded video data temporarily;

a third buffer to hold header data generated from said processor unit; and

a multiplex process unit to execute said system process according to an indication from said processor unit to sequentially output said encoded video data, said encoded audio data and said header data supplied from said first, second and third buffers, respectively, by an amount and in an order according to a system process parameter;

wherein

said processor unit includes an interrupt control circuit receiving at least one of said first, second and third timing signals to designate for an interrupt process one of said audio compression process, said first and second control processes in response to generation of each timing signal supplied as an input, and

said processor unit preferentially executes said interrupt process.

2. The encoding device according to

claim 1

wherein

said interrupt control circuit can change the designation of said interrupt process based on a predetermined priority when another of said timing signals is generated during an execution of said interrupt process.

3. The encoding device according to

claim 2

wherein

said interrupt control circuit receives said first, second and third timing signals.

4. The encoding device according to

claim 2

further comprising;

an internal bus connected to said processor unit to execute data transmission in said encoding device, wherein

said timing control unit includes a status register connected to said internal bus to indicate a state of said second timing signal;

said processor unit activates said audio encoding process according to a state of said status register; and

said interrupt control circuit designates one of said first and second control processes as said interrupt process in response to generation of said first and third timing signals, respectively.

5. The encoding device according to

claim 2

further comprising;

an internal bus connected to said processor unit to execute data transmission in said encoding device wherein

said timing control unit includes a status register connected to said internal bus to indicate a state of said third timing signal,

said processor unit activates said second control process according to a state of said status register, and

said interrupt control circuit designates one of said first control process and said audio encoding process as said interrupt process in response to generation of said first and second timing signals, respectively.

6. The encoding device according to

claim 2

further comprising;

an internal bus connected to said processor unit to execute data transmission in said encoding device, wherein

said timing control unit includes,

a first status register indicating a state of said second timing signal, and

a second status register indicating a state of said third timing signal,

said first and second status registers being connected to said internal bus

said processor unit activates said audio encoding process according to a state of said first status register,

said processor unit executes said second control process as said interrupt process in response to generation of said first timing signal and

said processor unit activates said second control process according to a state of said second status register at a time of completion of said interrupt process.

7. The encoding device according to

claim 2

further comprising;

an internal bus connected to said processor unit to execute data transmission in said encoding device, wherein

said timing control unit includes

a first status register indicating a state of said second timing signal, and

a second status register indicating a state of said third timing signal,

said first and second status registers being connected to said internal bus

said processor unit activates an operation of said second control process according to a state of said second status register,

said processor unit executes said first control process as said interrupt process in response to a generation of said first timing signal,

said processor unit activates said audio encoding process according to a state of said first status register at a time of completion of said interrupt process.

8. The encoding device according to

claim 1

further comprising;

an internal bus connected to said processor unit to execute data transmission in said encoding device, wherein

said video encoding process unit includes a first control register holding a control parameter for said video encoding process,

said multiplexing control unit includes a second control register holding said system process parameter,

said first and second control registers are connected to said internal bus and

said processor unit updates a content held in said first control register via said internal bus at a time of said first control process and updates a content held in said second control register via said internal bus at a time of said second control process.

9. The encoding device according to

claim 1

wherein

said timing control unit activates each of said first, second and third timing signals periodically,

said timing control unit generates at least one forced termination activation signal according to at least one of said first, second ant third timing signal, and

said processor unit indicates, at a timing of activation of said at least one forced termination activation signal, forced termination of an operation of a corresponding process if said operation has not been completed.

10. The encoding device according to

claim 9

wherein

each of said at least one of forced termination activation signals is activated at a timing a predetermined time period earlier than a next activation timing of a corresponding timing signal, and

said predetermined time period corresponds to a time period for executing a necessary process for said forced termination.

11. The encoding device according to

claim 1

further comprising;

an internal bus connected to said processor unit to execute data transmission in said encoding device, wherein

said timing control unit includes at least one signal delay circuit provided each corresponding to at least one of said first, second and third timing signals,

each of said signal delay circuit delays said corresponding timing signal by a delay time and outputs a resulting signal,

each of said signal delay circuit has a register connected to said internal bus to hold said delay time,

said processor unit receives an output signal from said corresponding signal delay circuit instead of said at least one of said first, second and third timing signals.

12. The encoding device according to

claim 1

wherein

said processor unit holds an internal state of said processor before execution of said interrupt process and recovers said held internal state at a time of completion of said interrupt process.

13. The encoding device according to

claim 1

wherein

said predetermined compression encoding standard is MPEG2 standard.

14. The encoding device according to

claim 1

wherein

said processor unit, said timing control unit, said first to third buffers and said multiplexing control unit are formed on a same semiconductor substrate.

15. The encoding device according to

claim 1

wherein

the encoding device further comprises

an output buffer to hold an output from said multiplex process unit to output the held output at a predetermined rate, and

said processor unit, said timing control unit, said first to third buffers, said output buffer and said multiplexing control unit are formed on a same semiconductor substrate.