Soi semiconductor integrated circuit for eliminating floating body effects in soi mosfets and method of fabricating the same

• US 20010031518A1
• Filed: 02/13/2001
• Published: 10/18/2001
• Est. Priority Date: 10/25/1999
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Sung-Dae, Kim, Min-Su, Kang, Hee-Sung, Kim, Byung-Sun, Kim, Kwang-Il, Kim, Young-Wug, Ko, Young-Gun
• Granted Patent: US 6,521,959 B2
• Time in Patent Office: Days
• US Class Current: 438/149
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

Claims

1. A silicon-on-insulator (SOI) semiconductor integrated circuit formed on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer, the integrated circuit comprising:

at least one isolated transistor active region comprising a predetermined region of the semiconductor layer;

a body line of the first conductivity type disposed at one side of the transistor active region, the body line including a portion of the semiconductor layer;

an isolation layer surrounding sidewalls of the transistor active region and the body line, the isolation layer being in contact with the buried insulating layer;

a body extension of the first conductivity type extended from a predetermined sidewall of the transistor active region and connected to the body line, the body extension being thinner than the transistor active region;

a body insulating layer formed on the body extension; and

an insulated gate pattern crossing over the transistor active region, the insulated gate pattern overlapping with the body insulating layer.

2. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, wherein the first conductivity type is one of P-type and N-type.

3. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, further comprising a metal suicide layer formed on the body line.

4. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, further comprising a gate insulating layer interposed between the insulated gate pattern and the transistor active region.

5. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, further comprising an insulating spacer formed on a sidewall of the insulated gate pattern.

6. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, wherein the gate pattern comprises a conductive gate electrode.

7. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 6

, further comprising a metal silicide layer formed on the gate electrode.

8. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, wherein the gate pattern comprises a conductive gate electrode and a capping insulating layer formed on the gate electrode.

9. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, further comprising:

a source region formed at the transistor active region and located at one side of the gate pattern; and

a drain region formed at the transistor active region and located at the other side of the gate pattern, the source and drain regions having a second conductivity type opposite to the first conductivity type.

10. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 9

, further comprising a metal silicide layer formed on the source and drain regions.

11. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, further comprising one of a ground line and a power line running over the body line, the one of the ground line and the power line being electrically connected to the body line.

12. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, wherein the body line is a straight line.

13. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 1

, wherein the at least one transistor active region comprises a plurality of transistor active regions.

14. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 13

, where in the plurality of transistor active regions are disposed at one side or both sides of the body line.

15. A method of fabricating a silicon-on-insulator (SOI) semiconductor integrated circuit on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer, the method comprising:

etching a predetermined region of the semiconductor layer, thereby forming a trench region defining at least one isolated transistor active region and a body line active region at one side of the transistor active region and concurrently leaving a semiconductor residue layer, which is thinner than the semiconductor layer, at a bottom of the trench region;

selectively etching the semiconductor residue layer until the buried insulating layer is exposed, thereby forming an isolation region and concurrently leaving a body extension of the first conductivity type connecting the transistor active region to the body line active region;

forming a body insulating layer and an isolation layer on the body extension and the exposed buried insulating layer, respectively;

forming an insulated gate pattern crossing over the transistor active region and overlapping with the body insulating layer; and

doping the body line active region with impurities of the first conductivity type to form a body line.

16. The method of

claim 15

, wherein forming the trench region and the semiconductor residue layer comprises:

forming at least one first trench mask pattern and a second trench mask pattern on the semiconductor layer; and

etching the semiconductor layer by a predetermined thickness which is thinner than the semiconductor layer using the first and second trench mask patterns as etching masks.

17. The method of

claim 16

, wherein forming the first and second trench mask patterns comprises:

forming a trench mask layer on the semiconductor layer; and

patterning the trench mask layer.

18. The method of

claim 17

, wherein the trench mask layer is formed by sequentially stacking a pad oxide layer and a pad nitride layer on the semiconductor layer.

19. The method of

claim 17

, wherein the trench mask layer is formed by sequentially stacking a pad oxide layer, a pad nitride layer and a hard mask layer on the semiconductor layer.

20. The method of

claim 16

, wherein forming the body insulating layer and the isolation layer comprises:

forming an insulating layer filling the trench region and the isolation region on an entire surface of the resultant structure having the isolation region;

planarizing the insulating layer until the first and second trench mask patterns are exposed; and

removing the first and second trench mask patterns to expose the transistor active region and the body line active region.

21. The method of

claim 15

, wherein forming the insulated gate pattern comprises:

forming a gate insulating layer on the transistor active region and the body line active region;

forming a gate material layer on an entire surface of the resultant structure having the gate insulating layer; and

patterning the gate material layer.

22. The method of

claim 21

, wherein the gate material layer is formed of a conductive layer.

23. The method of

claim 21

, wherein the gate material layer is formed by sequentially stacking a conductive layer and a capping insulating layer.

24. The method of

claim 15

, further comprising forming an insulating spacer on the sidewall of the insulated gate pattern.

25. The method of

claim 15

, further comprising forming a source region at the transistor active region which is located at one side of the gate pattern and a drain region at the transistor active region which is located at the other side of the gate pattern, the source and drain regions being doped with impurities of a second conductivity type opposite to the first conductivity type.

26. The method of

claim 24

, further comprising selectively forming a metal silicide layer on the body line and the transistor active region at both sides of the gate pattern.

27. The method of

claim 26

, wherein the metal silicide layer is formed using a salicide (self-aligned silicide) process.

28. The method of

claim 15

, further comprising:

forming an interlayer insulating layer on an entire surface of the resultant structure having the gate pattern and the body line;

patterning the interlayer insulating layer to form a contact hole exposing a portion of the body line; and

forming one of a power line and a ground line on the interlayer insulating layer, the one of the power line and the ground line being electrically connected to the body line through the contact hole.

29. A silicon-on-insulator (SOI) semiconductor integrated circuit formed on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer, the integrated circuit comprising:

a transistor active region comprising a predetermined region of the semiconductor layer;

at least one body contact active region spaced apart from the transistor active region, the body contact active region including a portion of the semiconductor layer;

a semiconductor residue layer disposed over the entire surface of the buried insulating layer between the transistor active region and the body contact active region, the semiconductor residue layer being thinner than the semiconductor layer;

a partial trench isolation layer surrounding upper sidewalls of the transistor active region and the body contact active region, the partial trench isolation layer being disposed on the semiconductor residue layer;

a full trench isolation layer interposed between the partial trench isolation layer and the transistor active region, the full trench isolation layer being in contact with the buried insulating layer;

a body extension of the first conductivity type extended from a predetermined sidewall of the semiconductor residue layer toward the transistor active region, the body extension electrically connecting the transistor active region to the semiconductor residue layer and being covered with the partial trench isolation layer; and

an insulated gate pattern crossing over the transistor active region, the insulated gate pattern being overlapped with the body extension.

30. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 29

, wherein the first conductivity type is one of P-type and N-type.

31. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 29

, wherein the semiconductor layer is a silicon layer.

32. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 29

, wherein the full trench isolation layer comprises a first full trench isolation layer and a second full trench isolation layer, which are separated each other.

33. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 32

, wherein the first and second full trench isolation layers are symmetrical to the insulated gate pattern each other.

34. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 29

, further comprises source/drain regions formed at the transistor active regions, which are located at both sides of the insulated gate pattern, the source/drain regions having a second conductivity type opposite to the first conductivity type and being in contact with the buried insulating layer.

35. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 34

, wherein the full trench isolation layer surrounds the source/drain regions.

36. The silicon-on-insulator (SOI) semiconductor integrated circuit of

claim 29

, further comprises a well contact region formed at the body contact active region, the well contact region having the first conductivity type.

37. A method of fabricating a silicon-on-insulator (SOI) semiconductor integrated circuit on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer, the method comprising:

etching a portion of the semiconductor layer to form a partial trench region defining a transistor active region and at least one body contact active region spaced apart from the transistor active region and leave a semiconductor residue layer, which is thinner than the semiconductor layer, between the transistor active region and the body contact active region;

etching a predetermined region of the semiconductor residue layer to form a full trench region exposing the buried insulating layer around the transistor active region and define a body extension extended from a portion of sidewall of the semiconductor residue layer toward the transistor active region, wherein the body extension connecting the transistor active region to the semiconductor residue layer;

forming a full trench isolation layer and a partial trench isolation layer inside the full trench region and the partial trench region, respectively; and

forming an insulated gate pattern crossing over the transistor active region, the insulated gate pattern being overlapped with the body extension.

38. The method of

claim 37

, wherein forming the partial trench region comprises:

forming a first trench mask pattern on the semiconductor layer, the first trench mask pattern including at least two separated mask patterns; and

etching the semiconductor layer by a predetermined thickness which is thinner than the semiconductor layer using the first trench mask pattern as an etching mask.

39. The method of

claim 38

, wherein forming the first trench mask pattern comprises:

forming a first trench mask layer on the semiconductor layer; and

patterning the first trench mask layer.

40. The method of

claim 39

, wherein the first trench mask layer is formed by sequentially stacking a pad oxide layer and a pad nitride layer on the semiconductor layer.

41. The method of

claim 38

, wherein forming the full trench region and defining the body extension comprises:

forming a second trench mask pattern exposing a portion of the semiconductor residue layer around the transistor active region and covering other portion of the semiconductor residue layer extended from a sidewall of the transistor active region;

etching the exposed semiconductor residue layer until the buried insulating layer is exposed using the first and second trench masks pattern as etching masks; and

removing the second trench mask pattern.

42. The method of

claim 41

, wherein forming the full trench isolation layer and the partial trench isolation layer comprises:

forming an insulating layer, filling the full trench region and the partial trench region, on an entire surface of the resultant structure where the second trench mask pattern is removed;

planarizing the insulating layer until the first trench mask pattern is exposed; and

removing the first trench mask pattern to expose the transistor active region and the body contact active region.

43. The method of

claim 37

, further comprises forming source/drain regions at the transistor active region which is located at both sides of the insulated gate pattern, the source/drain regions being doped with impurities of a second conductivity type opposite to the first conductivity type and being in contact with the buried insulating layer.

44. The method of

claim 43

, further comprises forming a well contact region at the body contact active region, the well contact region being doped with impurities of the first conductivity type.