Crown or stack capacitor with a monolithic fin structure

• US 20010031531A1
• Filed: 06/18/2001
• Published: 10/18/2001
• Est. Priority Date: 11/16/1998
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Liaw, Ing-Ruey
• Granted Patent: US 6,476,437 B2
• Time in Patent Office: Days
• US Class Current: 438/254
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold. Deposit a bulk or a thin film second monolithic conductive layer into the cavity to form a monolithic capacitor core with counterpart cantilevered ribs.

Claims

1. A process of forming an electrode comprising a capacitor core formed on a conductor sublayer formed on substrate, comprising:

forming a mold from a stack of silicon dioxide layers which are alternatingly undoped, doped, and undoped on said sublayer with said stack comprising a bottom layer formed on top of said conductor sublayer and each additional layer in said stack formed on a previous one of said layers in said stack,

patterning said silicon dioxide layers in said mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in said stack of silicon dioxide layers reaching down through said stack to be bottom of said stack,

differentially etching said silicon dioxide layers in said mold forming undercut edges in said doped silicon dioxide layers with said undoped silicon dioxide layers having cantilevered ribs projecting from said stacks into said cavity to complete said mold,

deposit a second conductive layer into said cavity forming a capacitor core with counterpart cantilevered ribs with a complementary pattern to said mold and said capacitor core having a top surface,

polish said capacitor core to remove said top surface of said core, and

remove said mold.

2. A process in accordance with

claim 1

wherein:

said mold is etched with a combination of hydrogen fluoride vapor and water vapor.

3. A process in accordance with

claim 1

wherein:

said dopant comprises boron and phosphorus, and

said mold is etched with a combination of hydrogen fluoride vapor and water vapor.

4. A process in accordance with

claim 1

wherein:

said capacitor core fills said cavity,

said mold is etched with a combination of hydrogen fluoride vapor and water vapor.

5. A process in accordance with

claim 1

wherein:

said capacitor core fills said cavity,

said dopant comprises boron and phosphorus, and

said mold is etched with a combination of hydrogen fluoride vapor and water vapor.

6. A process in accordance with

claim 1

wherein:

said core is a monolithic core,

said monolithic core is planarized by a CMP process which removes a top undoped layer of said mold whereby said monolithic core has a flat upper surface with a rib located at the top of said monolithic core, and

etch back said sublayer to separate said monolithic core from adjacent monolithic cores.

7. A process of forming an electrode comprising a capacitor core formed on a conductor layer formed on a substrate,

forming a mold from a stack of silicon dioxide layers which are alternatingly doped and undoped on said sublayer with said stack comprising a bottom layer formed on top of said sublayer and each additional layer in said stack formed on a previous one of said layers in said stack,

patterning said silicon dioxide layers in said mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in said stack of silicon dioxide layers reaching down through said stack to be bottom of said stack,

differentially etching said silicon dioxide layers in said mold forming undercut edges in said doped silicon dioxide layers with said undoped silicon dioxide layers having cantilevered ribs projecting from said stacks into said cavity to complete said mold,

deposit a thin layer of a second conductive layer into said cavity forming a thin capacitor core with counterpart cantilevered ribs with a complementary pattern to said mold and said capacitor core having a top surface,

deposit a layer filling said inner cavity,

polish said capacitor core to remove said top surface of said core, and

remove said photoresist and remove said mold.

8. A process in accordance with

claim 7

wherein:

said mold is etched with a combination of hydrogen fluoride vapor and water vapor.

9. A process in accordance with

claim 7

wherein:

said dopant comprises boron and phosphorus, and

said mold is etched with a combination of hydrogen fluoride vapor and water vapor.

10. A process in accordance with

claim 7

wherein:

said core is a monolithic core,

said monolithic core is planarized by a CMP process which removes a top undoped layer of said mold whereby said monolithic core has a flat upper surface with a rib located on top of said monolithic core, and

etch back said sublayer to separate said monolithic core from adjacent monolithic cores.

22. A process in accordance with

claim 7

wherein:

said dopant comprises boron and phosphorus, and

said mold is etched with a combination of hydrogen fluoride vapor and water vapor,

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride, and

said second conductive layer has a thickness from about 500 Å

to about 1,000 Å

.

11. A process of forming an electrode comprising a capacitor core formed on a semiconductor device comprising:

forming a sublayer of a conductor layer in contact with a plug which contacts a doped region in said semiconductor substrate,

forming a mold from a stack of silicon dioxide layers which are alternatingly doped and undoped on said sublayer with said stack comprising a bottom layer formed on top of said sublayer and each additional layer in said stack formed on a previous one of said layers in said stack,

patterning said silicon dioxide layers in said mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in said stack of silicon dioxide layers reaching down through said stack to be bottom of said stack,

differentially etching said silicon dioxide layers in said mold forming undercut edges in said doped silicon dioxide layers with said undoped silicon dioxide layers having cantilevered ribs projecting from said stacks into said cavity to complete said mold,

deposit a second conductive layer into said cavity forming a capacitor core with counterpart cantilevered ribs with a complementary pattern to said mold and said capacitor core having a top surface,

polish said capacitor core to remove said top surface of said core, and

remove said mold.

12. A process in accordance with

claim 11

wherein:

said core is a monolithic core,

said monolithic core is planarized by a CMP process which removes a top undoped layer of said mold whereby said monolithic core has a flat upper surface with a rib located on top of said monolithic core, and

etch back said sublayer to separate said monolithic core from adjacent monolithic cores.

13. A process in accordance with

claim 11

wherein:

said dopant comprises boron and phosphorus, and

etching said mold.

14. A process in accordance with

claim 11

wherein:

said capacitor core fills said cavity, and

etching said mold.

15. A process in accordance with

claim 11

wherein:

said capacitor core fills said cavity,

said dopant comprises boron and phosphorus, and

etching said mold with a combination of hydrogen fluoride vapor and water vapor.

16. A process in accordance with

claim 11

wherein:

etching said mold with a combination of hydrogen fluoride vapor and water vapor.

17. A process of forming an electrode comprising a capacitor core formed on a semiconductor device comprising:

forming a sublayer of a conductor layer in contact with a plug which contacts one of said region in said semiconductor substrate,

forming a mold from a stack of silicon dioxide layers which are alternatingly doped and undoped on said sublayer with said stack comprising a bottom layer formed on top of said sublayer and each additional layer in said stack formed on a previous one of said layers in said stack,

patterning said silicon dioxide layers in said mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in said stack of silicon dioxide layers reaching down through said stack to be bottom of said stack,

differentially etching said silicon dioxide layers in said mold forming undercut edges in said doped silicon dioxide layers with said undoped silicon dioxide layers having cantilevered ribs projecting from said stacks into said cavity to complete said mold,

deposit a thin layer of a second conductive layer into said cavity forming a thin capacitor core with counterpart cantilevered ribs with a complementary pattern to said mold and said capacitor core having a top surface,

deposit a layer filling said inner cavity;

polish said capacitor core to remove said top surface of said core;

remove said photoresist; and

remove said mold.

18. A process in accordance with

claim 17

wherein:

said mold is etched with a combination of hydrogen fluoride vapor and water vapor.

19. A process in accordance with

claim 17

wherein:

said dopant comprises boron and phosphorus, and

said mold is etched with a combination of hydrogen fluoride vapor and water vapor.

20. A process in accordance with

claim 17

wherein:

said core is planarized by a CMP process which removes a top undoped layer of said mold whereby said core has a flat upper surface with a rib located on top of said core, and

etch back said sublayer to separate said core from adjacent cores.

21. A process in accordance with

claim 17

wherein:

said mold is etched with a combination of hydrogen fluoride vapor and water vapor,

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride, and

said second conductive layer has a thickness from about 500 Å

to about 1,000 Å

.

23. A process in accordance with

claim 17

wherein:

said second conductive layer is formed into a monolithic core,

said monolithic core is planarized by a CMP process which removes a top undoped layer of said mold whereby said monolithic core has a flat upper surface with a rib located on top of said monolithic core,

etch back said sublayer to separate said monolithic core from adjacent monolithic cores,

said monolithic core is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride, and

said monolithic core has a thickness from about 500 Å

to about 1,000 Å

.

24. A monolithic capacitor core formed on a substrate comprising:

a sublayer comprising a first conductive layer formed on said substrate, and

a second conductive layer formed into a monolithic monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core.

25. The monolithic capacitor core of

claim 24

wherein:

said second conductive layer is formed into a hollow monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core and a base covering said first conductive layer.

26. The monolithic capacitor core of

claim 24

wherein:

said second conductive layer is formed as a solid monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core and said monolithic core covering said first conductive layer.

27. The monolithic capacitor core of

claim 24

wherein:

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride.

28. The monolithic capacitor core of

claim 24

wherein:

said second conductive layer is formed into a hollow monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core and a base covering said first conductive layer, and

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride.

29. The monolithic capacitor core of

claim 24

wherein:

said second conductive layer is formed as a solid monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core,

said monolithic core covering said first conductive layer; and

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride.

30. The monolithic capacitor core of

claim 24

wherein:

said second conductive layer is formed into a hollow monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core and a base covering said first conductive layer,

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride, and

said second conductive layer has a thickness from about 500 Å

to about 1,000 Å

.

31. A monolithic capacitor core formed on a semiconductor device comprising:

a sublayer first conductive layer in contact with a plug which contacts one of said region in said semiconductor substrate,

a second conductive layer formed into a monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core,

said monolithic capacitor core having a cantilevered top surface projecting from said exterior sidewall of said monolithic core.

32. The monolithic capacitor core of

claim 31

wherein:

said second conductive layer is formed into a hollow monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core and a base covering said first conductive layer.

33. The monolithic capacitor core of

claim 31

wherein:

said second conductive layer is formed as a solid monolithic capacitor core with cantilevered ribs projecting from exterior sidewalls of said monolithic core and said monolithic core covering said first conductive layer.

34. The monolithic capacitor core of

claim 31

wherein:

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride.

35. The monolithic capacitor core of

claim 31

wherein:

said second conductive layer is formed into a hollow monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core and a base covering said first conductive layer, and

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride.

36. The monolithic capacitor core of

claim 31

wherein:

said second conductive layer is formed as a solid monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core and said monolithic core covering said first conductive layer, and

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride.

37. The monolithic capacitor core of

claim 31

wherein:

said second conductive layer is formed into a hollow monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of said monolithic core and a base covering said first conductive layer,

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride, and

said second conductive layer has a thickness from about 500 Å

to about 1,000 Å

.

38. The monolithic capacitor core of

claim 31

wherein:

said second conductive layer is formed as a plurality of solid monolithic capacitor cores having said cantilevered ribs projecting from exterior sidewalls of said monolithic core and said monolithic core covering said first conductive layer,

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride, and

said sublayer having been formed into separated portions isolating said monolithic cores from adjacent ones of said monolithic cores.

39. The monolithic capacitor core of

claim 31

wherein:

said second conductive layer is formed as a plurality of hollow monolithic capacitor cores having said cantilevered ribs projecting from exterior sidewalls of said monolithic core and said monolithic core covering said first conductive layer,

said second conductive layer is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride, and

said sublayer having been formed into separated portions isolating said monolithic cores from adjacent ones of said monolithic cores.