Super-junction semiconductor device and method of manufacturing the same

• US 20010032998A1
• Filed: 03/19/2001
• Published: 10/25/2001
• Est. Priority Date: 03/17/2000
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Sato, Takahiro, Onishi, Yasuhiko, Iwamoto, Susumu, Ueno, Katsunori, Fujihira, Tatsuhiko
• Granted Patent: US 6,677,643 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A super-junction semiconductor is provided that facilitates easy mass-production thereof, reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity thereof. The super-junction semiconductor device includes a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer on low resistance layer, and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer including regions of a first conductivity type and regions of a second conductivity type arranged alternately with each other. The second alternating conductivity type layer including regions of the first conductivity type and regions of the second conductivity type arranged alternately with each other. The spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer.

Claims

1. A semiconductor device comprising:

a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface;

a layer with low electrical resistance on the side of the second major surface;

a first alternating conductivity type layer above the layer with low electrical resistance, the first alternating conductivity type layer comprising one or more first regions of a first conductivity type and second regions of a second conductivity type, the first regions and the second regions forming first pn-junctions therebetween; and

a second alternating conductivity type layer in plane contact with the first alternating conductivity type layer, the second alternating conductivity type layer comprising one or more third regions of the first conductivity type and fourth regions of the second conductivity type the third regions and the fourth regions forming second pn-junctions therebetween;

the second pn-junctions in the second alternating conductivity type layer being spaced apart from each other by a wider spacing than the first pn-junctions in the first alternating conductivity type layer.

2. The semiconductor device according to

claim 1

, wherein the boundary between the first alternating conductivity type layer and the second alternating conductivity type layer extends subtantially parallel to the first major surface.

3. The semiconductor device according to

claim 1

, wherein surfaces of the first pn-junctions in the first alternating conductivity type layer are substantially parallel to surfaces of the second pn-junctions in the second alternating conductivity type layer.

4. The semiconductor device according to

claim 1

, wherein the second alternating conductivity type layer is between the first alternating conductivity type layer and the first major surface.

5. The semiconductor device according to

claim 1

, wherein surfaces of the first pn-junctions in the first alternating conductivity type layer are substantially perpendicular to surfaces of the second pn-junctions in the second alternating conductivity type layer.

6. The semiconductor device according to

claim 1

, wherein the first regions of the first conductivity type in the first alternating conductivity type layer are connected to the third regions of the first conductivity type in the second alternating conductivity type layer, and the second regions of the second conductivity type in the first alternating conductivity type layer are connected to the fourth regions of the second conductivity type in the second alternating conductivity type layer.

7. The semiconductor device according to

claim 1

, wherein the third regions and the fourth regions in second alternating conductivity type layer are arranged differently from the first regions and the second regions in first alternating conductivity type layer.

8. The method of manufacturing a semiconductor device including a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface;

a layer with low electrical resistance on the side of the second major surface;

a first alternating conductivity type layer above the layer with low electrical resistance, the first alternating conductivity type layer including one or more first regions of a first conductivity type and second regions of a second conductivity type, the first regions and the second regions forming first pn-junctions therebetween; and

a second alternating conductivity type layer in plane contact with the first alternating conductivity type layer, the second alternating conductivity type layer including one or more third regions of the first conductivity type and fourth regions of the second conductivity type, the third regions and the fourth regions forming second pn-junctions therebetween;

the second pn-junctions in the second alternating conductivity type layer being spaced part from each other more widely than the first pn-junctions in the first alternating conductivity type layer, the method comprising the steps of

(a) forming an epitaxial layer;

(b) implanting an inpurty of the second conductivity type selectively into first surface portions of the epitaxial layer;

(c) implanting an impurity of the first conductivity type selectively into second surface portions of the epitaxial layer;

(d) repeating the steps (a) through (c); and

(e) thermally driving all the implanted impurities, whereby to form the first alternating conductivty type layer and the second alternating conductivity type layer.