Stacked integrated circuits

• US 20010033509A1
• Filed: 05/14/2001
• Published: 10/25/2001
• Est. Priority Date: 11/23/1998
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 6,395,630 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H05K 1/0219 Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards

Abstract

System modules are described which include a stack of interconnected semiconductor dies. The semiconductor dies are interconnected by micro bump bonding of coaxial lines that extend through the thickness of the various dies. The coaxial lines also are selectively connected to integrated circuits housed within the dies. In one embodiment, a number of memory dies are interconnected in this manner to provide a memory module.

Claims

1. A system module, comprising:

a plurality of stacked semiconductor chips each including an integrated circuit;

each semiconductor chip including a plurality of vias formed through the thickness of the semiconductor chip;

a plurality of conductors, each conductor having first and second opposite ends and formed in one of the vias;

each conductor selectively interconnected with the integrated circuit of its semiconductor chip; and

a plurality of microbumps, each microbump formed on an end of a selected conductor so as to interconnect the integrated circuits of the plurality of stacked semiconductor chips.

2. The system module of

claim 1

, wherein the integrated circuits comprise memory circuits.

3. The system module of

claim 1

, wherein each conductor comprises a coaxial conductor.

4. The system module of

claim 1

, wherein the microbumps comprise controlled-collapse chip connections (C-4) solder pads.

5. The system module of

claim 1

, wherein each conductor comprises:

an outer conductive layer formed along a wall of a selected via;

an insulator layer; and

an inner conductive layer substantially parallel to and separated from the outer conductive layer by the insulator layer.

6. The system module of

claim 1

, wherein the semiconductor chips each comprise a die having a random access memory circuit.

7. A memory module, comprising:

a plurality of stacked semiconductor chips each including a memory circuit;

each semiconductor chip including a plurality of vias formed through the thickness of the semiconductor chip;

a plurality of coaxial conductors, each having first and second opposite ends and formed in one of the vias;

each coaxial conductor selectively interconnected with the memory circuit of its semiconductor chip; and

a plurality of microbumps, each microbump formed on an end of a selected conductor so as to interconnect the memory circuits of the plurality of stacked semiconductor chips.

8. The memory module of

claim 7

, wherein the microbumps comprise controlled-collapse chip connections (C-4) solder pads.

9. The memory module of

claim 7

, wherein each conductor comprises:

an outer conductive layer formed along a wall of a selected via;

an insulator layer; and

an inner conductive layer substantially parallel to and separated from the outer conductive layer by the insulator layer.

10. The memory module of

claim 9

, wherein the outer conductive layer comprises a layer of doped semiconductor material.

11. The memory module of

claim 9

, wherein the outer conductive layer comprises a metal layer that lines a surface of the via.

12. A method for interconnecting integrated circuits to form a system module, the method comprising:

selectively forming microbumps on first and second opposite surfaces of a plurality of semiconductor chips, each semiconductor chip having an integrated circuit that is formed in at least one working surface of the semiconductor chip;

selectively aligning the plurality of semiconductor chips to form a stack; and

for each interface between adjacent semiconductor chips in the stack, bonding the microbumps on the surface of one semiconductor chip with the microbumps on the surface of the other, adjacent semiconductor chip.

13. The method of

claim 12

, wherein selectively forming microbumps comprises selectively forming controlled-collapse chip connection (C-4) solder pads.

14. The method of

claim 12

, wherein selectively aligning the plurality of semiconductor chips comprises aligning corresponding microbumps on adjacent surfaces of the plurality of semiconductor chips in the stack.

15. The method of

claim 12

, wherein bonding the microbumps comprises bringing the microbumps into contact with each other.

16. A method for interconnecting memory circuits to form a memory module, the method comprising:

selectively forming microbumps on first and second opposite surfaces of a plurality of semiconductor chips, each semiconductor chip having a memory circuit that is formed in at least one working surface of the semiconductor chip;

selectively aligning the plurality of semiconductor chips to form a stack; and

for each interface between adjacent semiconductor chips in the stack, bonding the microbumps on the surface of one semiconductor chip with the microbumps on the surface of the other, adjacent semiconductor chip.

17. The method of

claim 16

, wherein selectively forming microbumps comprises selectively forming controlled-collapse chip connection (C-4) solder pads.

18. The method of

claim 16

, wherein selectively aligning the plurality of semiconductor chips comprises aligning corresponding microbumps on adjacent surfaces of the plurality of semiconductor chips in the stack.

19. The method of

claim 16

, wherein bonding the microbumps comprises bringing the microbumps into contact with each other.

20. A system, comprising:

a processor circuit;

a memory module that is communicatively coupled to the processor circuit; and

wherein the memory module includes a plurality of semiconductor memory chips that are coupled in a stack by microbump bonding and coaxial conductors that extend through the thickness of the semiconductor chips.

21. The system of

claim 20

, wherein the memory module comprises:

a plurality of vias formed through the thickness of each semiconductor memory chip;

a plurality of coaxial conductors, each having first and second opposite ends and formed in one of the plurality of vias;

each coaxial conductor selectively interconnected with a memory circuit of its semiconductor memory chip; and

a plurality of microbumps, each microbump formed on an end of a selected conductor so as to interconnect the memory circuits of the plurality of stacked semiconductor memory chips.

22. The system of

claim 21

, wherein the microbumps comprise controlled-collapse chip connections (C-4) solder pads.

23. The system of

claim 21

, wherein each conductor comprises:

an outer conductive layer formed along a wall of a selected via;

an insulator layer; and

an inner conductive layer substantially parallel to and separated from the outer conductive layer by the insulator layer.

24. The system of

claim 21

, wherein the outer conductive layer comprises a layer of doped semiconductor material.

25. The system of

claim 21

, wherein the outer conductive layer comprises a metal layer that lines a surface of the via.

26. A memory cube, comprising:

a plurality of semiconductor dies;

each semiconductor die including a memory circuit formed in a working surface of the semiconductor die;

a plurality of coaxial conductors formed through the thickness of each semiconductor die and having first and second opposite ends;

a metallization layer formed on the working surface of each semiconductor die to selectively interconnect the coaxial conductors with the memory circuit;

a plurality of microbumps on each semiconductor die, each microbump coupled to an end of a selected coaxial conductor; and

wherein the semiconductor dies are disposed in a stack with microbumps on surfaces of adjacent semiconductor dies being bonded together to interconnect the memory circuits in the memory cube.

27. The memory cube of

claim 26

, wherein the microbumps comprise controlled-collapse chip connections (C-4) solder pads.

28. The memory cube of

claim 26

, wherein each conductor comprises:

an outer conductive layer formed along a wall of a selected via;

an insulator layer; and

an inner conductive layer substantially parallel to and separated from the outer conductive layer by the insulator layer.

29. The memory cube of

claim 26

, wherein the outer conductive layer comprises a layer of doped semiconductor material.

30. The memory cube of

claim 26

, wherein the outer conductive layer comprises a metal layer that lines a surface of the via.

31. The memory cube of

claim 26

, wherein the microbumps are formed around a periphery of the semiconductor die.