Hardmask designs for dry etching FeRAM capacitor stacks

• US 20010034106A1
• Filed: 12/19/2000
• Published: 10/25/2001
• Est. Priority Date: 12/22/1999
• Status: Active Grant

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.), Texas Instruments, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Moise, Theodore, Summerfelt, Scott R., Colombo, Luigi, Xing, Guoqiang, Gilbert, Stephen R.
• Granted Patent: US 6,534,809 B2
• Time in Patent Office: Days
• US Class Current: 438/396
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material

Abstract

An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material (304 of FIG. 4a); a top electrode formed over the bottom electrode and comprised of a first electrode material (306 and 308 of FIG. 4a); a ferroelectric material (306 of FIG. 4a) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer (402 of FIG. 4a) and a top hardmask layer (408 of FIG. 4a) formed on the bottom hardmask layer, the top hardmask layer able to with stand etchants used to etch the bottom electrode, the top electrode, and the ferroelectric material to leave the bottom hardmask layer substantially unremoved during the etch and the bottom hardmask layer being comprised of a conductive material which substantially acts as a hydrogen diffusion barrier.

Claims

1. A ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising:

a bottom electrode formed over the semiconductor substrate, said bottom electrode comprised of a bottom electrode material;

a top electrode formed over said bottom electrode and comprised of a first electrode material;

a ferroelectric material situated between said top electrode and said bottom electrode; and

a hardmask formed on said top electrode and comprising a bottom hardmask layer and a top hardmask layer formed on said bottom hardmask layer, said top hardmask layer able to with stand etchants used to etch said bottom electrode, said top electrode, and said ferroelectric material to leave said bottom hardmask layer substantially unremoved during said etch and said bottom hardmask layer being comprised of a conductive material which substantially acts as a hydrogen diffusion barrier.

2. The ferroelectric capacitor of

claim 1

, wherein said bottom hardmask layer is comprised of a material selected from the group consisting of:

TiN, TiAlN, TaN, CrN, HfN, ZrN, TaSiN, TiSiN, TaAlN, CrAlN and any stack or combination thereof.

3. The ferroelectric capacitor of

claim 1

, wherein said top hardmask layer is comprised of a material selected from the group consisting of:

doped SiO₂, undoped SiO₂, SiN, SiON, SiC, SiCN, SiCON, a low K dielectric, and any stack or combination thereof.

4. The ferroelectric capacitor of

claim 1

, wherein said top hardmask layer is comprised of a first top hardmask layer situated on a second top hardmask layer.

5. The ferroelectric capacitor of

claim 4

, wherein said first top hardmask material is comprised of a material selected from the group consisting of:

Ti, TiN, TiAl, TiAlN, Al, AlN, Ta, TaN, Zr, ZrN, Hf, HfN, TiSi, TiSiN, TaSi, TaSiN, TaAl, TaAlN, CrAl, CrAlN, SiO₂ (doped or undoped), SiN, SiON, SiC, SiCN, SiCON, or a low K dielectric, and any stack or combination thereof.

6. The ferroelectric capacitor of

claim 4

, wherein said second top hardmask layer is comprised of a material selected from the group consisting of:

AlOx, TiO_x, TiAlO_x, TaO_x, CrO_x, HfO_x, ZrO_x, TaSiO_x, TiSiO_x, TaAlO_x, CrAlO_x, Pt, Ir, IrOx, Rh, RhOx, Au, Ag, Pd, PdO_x, and any stack or combination thereof.

7. The ferroelectric capacitor of

claim 1

, wherein said top electrode is comprised of a material selected from the group consisting of:

iridium, iridium oxide, and any combination or stack thereof.

8. The ferroelectric capacitor of

claim 1

, wherein said bottom electrode is comprised of a material selected from the group consisting of:

iridium, iridium oxide, and any combination or stack thereof.

9. The ferroelectric capacitor of

claim 1

, wherein said ferroelectric material is comprised of PZT.

10. A ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising:

a bottom diffusion barrier formed over the semiconductor substrate, said bottom diffusion barrier comprised of a first conductive material which substantially acts as a hydrogen diffusion barrier;

a bottom electrode formed on said bottom diffusion barrier and comprised of a bottom electrode material;

a top electrode formed over said bottom electrode and comprised of a first electrode material;

a ferroelectric material situated between said top electrode and said bottom electrode; and

a hardmask formed on said top electrode and comprising a bottom hardmask layer and a top hardmask layer formed on said bottom hardmask layer, said top hardmask layer able to with stand etchants used to etch said bottom diffusion barrier, said bottom electrode, said top electrode, and said ferroelectric material so as to leave said bottom hardmask layer substantially unremoved during said etch and said bottom hardmask layer being comprised of a second conductive material which substantially acts as a hydrogen diffusion barrier.

11. The ferroelectric capacitor of

claim 10

, wherein said bottom hardmask layer is comprised of a material selected from the group consisting of:

TiN, TiAlN, TaN, CrN, HfN, ZrN, TaSiN, TiSiN, TaAlN, CrAlN and any stack or combination thereof.

12. The ferroelectric capacitor of

claim 10

, wherein said top hardmask layer is comprised of a material selected from the group consisting of:

doped SiO₂, undoped SiO₂, SiN, SiON, SiC, SiCN, SiCON, a low K dielectric, and any stack or combination thereof.

13. The ferroelectric capacitor of

claim 10

, wherein said top hardmask layer is comprised of a first top hardmask layer situated on a second top hardmask layer.

14. The ferroelectric capacitor of

claim 13

, wherein said first top hardmask material is comprised of a material selected from the group consisting of:

Ti, TiN, TiAl, TiAlN, Al, AlN, Ta, TaN, Zr, ZrN, Hf, HfN, TiSi, TiSiN, TaSi, TaSiN, TaAl, TaAlN, CrAl, CrAlN, SiO₂ (doped or undoped), SiN, SiON, SiC, SiCN, SiCON, or a low K dielectric, and any stack or combination thereof.

15. The ferroelectric capacitor of

claim 13

, wherein said second top hardmask layer is comprised of a material selected from the group consisting of:

AlOx, TiO_x, TiAlO_x, TaO_x, CrO_x, HfO_x, ZrO_x, TaSiO_x, TiSiO_x, TaAlO_x, CrAlO_x, Pt, Ir, IrOx, Rh, RhOx, Au, Ag, Pd, PdO_x, and any stack or combination thereof.

16. The ferroelectric capacitor of

claim 10

, wherein said top electrode is comprised of a material selected from the group consisting of:

iridium, iridium oxide, and any combination or stack thereof.

17. The ferroelectric capacitor of

claim 10

, wherein said bottom electrode is comprised of a material selected from the group consisting of:

iridium, iridium oxide, and any combination or stack thereof.

18. The ferroelectric capacitor of

claim 10

, wherein said ferroelectric material is comprised of PZT.

19. The ferroelectric capacitor of

claim 10

, wherein said bottom diffusion barrier is comprised of a material selected from the group consisting of:

TiN, TiAlN, TaN, CrN, HfN, ZrN, TaSiN, TiSiN, TaAlN, CrAlN and any stack or combination thereof.