Computer system

• US 20010034860A1
• Filed: 02/07/2001
• Published: 10/25/2001
• Est. Priority Date: 04/20/2000
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Phillips, Mark
• Granted Patent: US 6,738,927 B2
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

A register of a processor is set to one value when a host is connected to the processor and to a second value when no host is connected. The processor then starts execution after reading the register contents, and if it finds that the second value is stored it writes a set value to a pointer storage location. When the one value is stored, it leaves the content of the pointer location unaffected.

Claims

1. A method of operating a target system having a digital signal processor, said digital signal processor having plural registers, the target system further having a link connectable to a host computer for debugging said target system, wherein said target system further has a memory having plural addressable locations, one of said locations being designated for storage therein of pointer information indicative of the entry point of a subroutine useable in debugging by said host computer, and other locations storing an application program, the method comprising:

setting the contents of a predetermined one of said registers of said digital signal processor to a first value when said host is connected to said link, and to a second value when said host is not connected to said link;

starting execution by said digital signal processor of said application program on said target system, wherein said step of starting execution comprises;

reading the content of said predetermined one of said registers;

when said one register stores said second value, writing a predetermined value to said one of said locations;

when said one register stores said first value, leaving the contents of said one of said locations unchanged.

2. The method of

claim 1

further comprising, when said host is connected to said link, and prior to said step of setting the contents of said predetermined one of said registers to said first value:

storing to said one of said locations pointer information indicative of said entry point.

3. The method of

claim 1

further comprising loading said subroutine by said host to said memory, and storing said pointer information indicative of the entry point of said subroutine.

4. The method of

claim 1

further comprising dynamically loading said subroutine by said host to said memory, whereby said host determines said entry point of said subroutine, and writing data by said host to said one of said locations, said data comprising said pointer information indicative of the entry point of said subroutine.

5. The method of

claim 1

wherein said target system further comprises reset logic, the method further comprising:

effecting a reset sequence of said digital signal processor, using said reset logic; and

thereafter setting said predetermined register to said second value.

6. The method of

claim 5

and further comprising, when said host is connected:

after setting said predetermined register to said second value, suspending operation of said digital signal processor;

setting said predetermined register to said first value; and

releasing said digital signal processor from the suspended state.

7. The method of

claim 6

and further comprising causing said digital signal processor to start from the suspended state at an address set by said host.

8. The method of

claim 5

, and further comprising when said host is not connected:

after said step of setting said predetermined register to said second value, starting said digital signal processor executing code of said application at a location determined by said target system.

9. The method of

claim 1

, wherein said step of setting said register comprises writing a single bit to said register, wherein said first value and said second value are complementary.

10. A computer system having a digital signal processor, said digital signal processor having plural registers, the system further having a link connectable to a host computer for debugging said system, wherein said system further has a memory having plural addressable locations, one of said locations being designated for storage therein of pointer information indicative of the entry point of a subroutine useable in debugging by said host computer, and other locations storing an application program, the system comprising:

reset circuitry for setting the contents of a predetermined one of said registers of said digital signal processor to a second value;

circuitry responsive to a host connected to said link for setting the contents of said register to a first value;

said digital signal processor comprising circuitry starting execution of said application, and further comprising determining circuitry for determining the content of said predetermined one of said registers; and

writing circuitry for writing a predetermined value to said one of said locations when said one register stores said second value, whereby when said one register stores the first value, the contents of said one of said locations remains unchanged.

11. The system of

claim 10

in combination with a host computer connected to said link, whereby said system is a target system, the combination further comprising circuitry in said host for loading said subroutine to said memory of said target system, and for storing said pointer information indicative of the entry point of said subroutine in said one location of said target system

12. The combination of

claim 11

wherein said host comprises a dynamic loader for dynamically loading said subroutine to said memory, whereby said host determines said entry point of said subroutine.

13. The system of

claim 10

further comprising reset logic for effecting a reset sequence of said digital signal processor;

said writing circuitry being operative thereafter to writing said second value to said predetermined register.

14. The system of

claim 13

in combination with a host connected to said link, comprising control circuitry in said host for suspending operation of said digital signal processor, after said writing circuitry has written said second value to said predetermined register, and setting circuitry for setting said predetermined register to said first value, said control circuitry being further operable to release said digital signal processor from the suspended state

15. The combination of

claim 14

further comprising initialisation circuitry for supplying from said host a starting address to said digital signal processor whereby said digital signal processor starts from the suspended state at said starting address.

16. The system of

claim 13

further comprising starting circuitry for starting said digital signal processor executing code of said application at a location determined by said target system when said host is not connected, after said writing circuitry writes said second value to said predetermined register.