Output driver circuit with well-controlled output impedance

• US 20010035768A1
• Filed: 03/06/2001
• Published: 11/01/2001
• Est. Priority Date: 10/26/1998
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Donnelly, Kevin S., Zerbe, Jared LeVan, Garlepp, Bruno Werner
• Granted Patent: US 6,448,813 B2
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

An output driver circuit for driving a signal onto a signal line. The output driver circuit comprises at least one driver circuit and a passive network. The passive network is configured to limit the variation in the output impedance of the output driver circuit. The output driver circuit thus provides an output impedance that closely matches the loaded impedance of the signal line at all times so as to minimize secondary reflections on the signal line.

Claims

1. An output driver circuit including an output for coupling to a conductor of a signal line, the output having an output impedance, the output driver circuit comprising:

a driver circuit having an output; and

a passive network coupled to the output of the driver circuit and to the output of the output driver circuit, the passive network configured to limit variation in the output impedance to a predefined range while the output driver circuit operates within a predefined range of expected operating conditions.

2. The output driver circuit of

claim 1

, wherein the passive network comprises:

a series resistor including a first end coupled to the output of the driver circuit and a second end;

a parallel resistor including a first end coupled to the second end of the series resistor and a second end coupled to a voltage supply; and

an output coupled to the second end of the series resistor and to the first end of the parallel resistor for coupling to the conductor.

3. The output driver circuit of

claim 2

, wherein the passive network further comprises:

a capacitor coupled between the second end of the parallel resistor and the voltage supply.

4. An electronic system for generating and transmitting a digital signal, comprising:

(1) an output driver circuit, comprising;

(a) a driver circuit having an output;

(b) a passive network coupled to the output of the driver circuit, comprising;

(i) a series resistor including a first end coupled to the output of the driver circuit and a second end;

(ii) a parallel resistor including a first end coupled to the second end of the series resistor and a second end;

(iii) a capacitor coupled between the second end of the parallel resistor and a first voltage supply; and

(iv) an output coupled to the second end of the series resistor and to the first end of the parallel resistor for coupling to the conductor; and

(c) an output coupled to the output of the passive network, the output having an output impedance; and

(2) a signal line, comprising;

(a) a conductor including a first end coupled to the output of the output driver circuit and a second end;

(b) a resistor including a first end coupled to the second end of the conductor and a second end; and

(c) a capacitor coupled between the second end of the resistor and a second voltage supply.

5. An output driver circuit including first and second outputs for coupling to first and second conductors, respectively, of a differential signal line, the first and second outputs having first and second output impedances, respectively, the output driver circuit comprising:

a first driver circuit having an output;

a second driver circuit having an output; and

a passive network coupled to the outputs of the first and second driver circuits and to the first and second outputs of the output driver circuit, the passive network configured to limit variation in the first and second output impedances to a predefined range while the output driver circuit operates within a predefined range of expected operating conditions.

6. The output driver circuit of

claim 5

, wherein:

the first and second conductors have first and second loaded impedances, respectively; and

the first and second output impedances do not fall below about 75 percent and do not exceed about 150 percent of the first and second loaded impedances, respectively, while the output driver circuit operates within the predefined range of expected operating conditions.

7. An output driver circuit for coupling to a differential signal line having a first conductor and a second conductor, comprising:

a first driver circuit having an input and an output;

a second driver circuit having an input and an output; and

a passive network coupled to the outputs of the first and second driver circuits and including a first output for coupling to the first conductor and a second output for coupling to the second conductor, comprising;

a first parallel resistor including a first end coupled to the first output of the passive network and a second end coupled to a differential ground node; and

a second parallel resistor including a first end coupled to the second output of the passive network and a second end coupled to the differential ground node.

8. The output driver circuit of

claim 7

, wherein the passive network further comprises:

a capacitor including a first end coupled to the differential ground node and a second end coupled to a voltage supply.

9. The output driver circuit of

claim 7

, wherein:

the first and second driver circuits each comprise a p-channel transistor and an n-channel transistor connected in a CMOS inverter configuration; and

the passive network further comprises;

a first series resistor including a first end connected to the output of the first driver circuit and a second end connected to the first end of the first parallel resistor; and

a second series resistor including a first end connected to the output of the second driver circuit and a second end connected to the first end of the second parallel resistor.

10. The output driver circuit of

claim 9

, further comprising:

a first predriver including an input connected to the input of the first driver circuit and an output connected to the gate of the p-channel transistor of the first driver circuit, the first predriver having a first and second delay from its input to its output for a low-to-high and high-to-low output transition, respectively;

a second predriver including an input connected to the input of the first driver circuit and an output connected to the gate of the n-channel transistor of the first driver circuit, the second predriver having a third and fourth delay from its input to its output for a low-to-high and high-to-low output transition, respectively, wherein the third delay is larger than the first delay and the second delay is larger than the fourth delay;

a third predriver including an input connected to the input of the second driver circuit and an output connected to the gate of the p-channel transistor of the second driver circuit, the third predriver having a fifth and sixth delay from its input to its output for a low-to-high and high-to-low output transition, respectively; and

a fourth predriver including an input connected to the input of the second driver circuit and an output connected to the gate of the n-channel transistor of the second driver circuit, the fourth predriver having a seventh and eighth delay from its input to its output for a low-to-high and high-to-low output transition, respectively, wherein the seventh delay is larger than the fifth delay and the sixth delay is larger than the eighth delay.

11. The output driver circuit of

claim 7

, wherein:

(1) the first driver circuit comprises;

a first p-channel transistor including a source coupled to a power supply, a drain and a gate coupled to the input of the first driver circuit;

a first series resistor including a first end coupled to the drain of the first p-channel transistor and a second end coupled to the output of the first driver circuit;

a second series resistor including a first end coupled to the output of the first driver circuit and a second end; and

a first n-channel transistor including a drain coupled to the second end of the second series resistor, a source coupled to a ground supply and a gate coupled to the input of the first driver circuit; and

(2) the second driver circuit comprises;

a second p-channel transistor including a source coupled to the power supply, a drain and a gate coupled to the input of the second driver circuit;

a third series resistor including a first end coupled to the drain of the second p-channel transistor and a second end coupled to the output of the second driver circuit;

a fourth series resistor including a first end coupled to the output of the second driver circuit and a second end; and

a second n-channel transistor including a drain coupled to the second end of the fourth series resistor, a source coupled to the ground supply and a gate coupled to the input of the second driver circuit.

12. The output driver circuit of

claim 11

, further comprising:

a first predriver including an input connected to the input of the first driver circuit and an output connected to the gate of the first p-channel transistor, the first predriver having a first and second delay from its input to its output for a low-to-high and high-to-low output transition, respectively;

a second predriver including an input connected to the input of the first driver circuit and an output connected to the gate of the first n-channel transistor, the second predriver having a third and fourth delay from its input to its output for a low-to-high and high-to-low output transition, respectively, wherein the third delay is larger than the first delay and the second delay is larger than the fourth delay;

a third predriver including an input connected to the input of the second driver circuit and an output connected to the gate of the second p-channel transistor, the third predriver having a fifth and sixth delay from its input to its output for a low-to-high and high-to-low output transition, respectively; and

a fourth predriver including an input connected to the input of the second driver circuit and an output connected to the gate of the second n-channel transistor, the fourth predriver having a seventh and eighth delay from its input to its output for a low-to-high and high-to-low output transition, respectively, wherein the seventh delay is larger than the fifth delay and the sixth delay is larger than the eighth delay.

13. An electronic system for generating and transmitting a digital signal, comprising:

(1) an output driver circuit, comprising;

(a) a first driver circuit having an input and an output;

(b) a second driver circuit having an input and an output;

(c) a passive network coupled to the outputs of the first and second driver circuits, comprising;

(i) a first parallel resistor including a first end coupled to a first output of the passive network and a second end coupled to a first differential ground node; and

(ii) a second parallel resistor including a first end coupled to a second output of the passive network and a second end coupled to the first differential ground node; and

(d) first and second outputs coupled to the first and second outputs of the passive network, respectively; and

(2) a signal line, comprising;

(a) a first conductor including a first end coupled to the first output of the output driver circuit and a second end;

(b) a first resistor including a first end coupled to the second end of the first conductor and a second end coupled to a second differential ground node;

(c) a second conductor including a first end coupled to the second output of the output driver circuit and a second end; and

(d) a second resistor including a first end coupled to the second end of the second conductor and a second end coupled to the second differential ground node.

14. The electronic system of

claim 13

, further comprising a capacitor having a first end coupled to the second differential ground node and a second end coupled to a power supply.

15. An output driver circuit for coupling to a differential signal line having a first conductor and a second conductor, comprising:

a first output for coupling to a first end of the first conductor;

a first p-channel transistor including a source coupled to a power supply, a drain coupled to the first output and a gate for receiving a first drive signal having a voltage such that the first p-channel transistor operates in a saturation or cutoff region of operation only;

a first n-channel transistor including a drain coupled to the first output, a source coupled to a ground supply and a gate for receiving a second drive signal having a voltage such that the first n-channel transistor operates in a saturation or cutoff region of operation only;

a first resistor including a first end coupled to the first output and a second end coupled to a differential ground node;

a second output for coupling to a first end of the second conductor;

a second p-channel transistor including a source coupled to the power supply, a drain coupled to the second output and a gate for receiving a third drive signal having a voltage such that the second p-channel transistor operates in a saturation or cutoff region of operation only;

a second n-channel transistor including a drain coupled to the second output, a source coupled to the ground supply and a gate for receiving a fourth drive signal having a voltage such that the second n-channel transistor operates in a saturation or cutoff region of operation only; and

a second resistor including a first end coupled to the second output and a second end coupled to the differential ground node.

16. The output driver circuit of

claim 15

, further comprising:

a first predriver for receiving a first input signal and generating the first drive signal;

a second predriver for receiving the first input signal and generating the second drive signal;

a third predriver for receiving a second input signal and generating the third drive signal; and

a fourth predriver for receiving the second input signal and generating the fourth drive signal.

17. The output driver circuit of

claim 15

, further comprising:

a capacitor including a first end coupled to the differential ground node and a second end coupled to a voltage supply.