Semiconductor device and manufacturing method of the same

• US 20010036711A1
• Filed: 04/23/2001
• Published: 11/01/2001
• Est. Priority Date: 04/24/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Urushima, Michitaka
• Granted Patent: US 6,791,195 B2
• Time in Patent Office: Days
• US Class Current: 438/460
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73104 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/166 : Material
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Semiconductor device 3 comprises semiconductor chip 11, Au ball bumps 21 formed on pad electrodes 12 with a stud bump method, and thermoplastic adhesive layer 22 provided on the surface of semiconductor chip 11 on which pad electrodes 12 are formed, in which the tops of Au ball bumps 21 project from the surface of adhesive layer 22. Reliable bonding can be realized by forming the bumps for electrical connection and the adhesive resin having an adhesion function on the semiconductor chip. In addition, the present invention provides a method of bonding a copper foil to a semiconductor wafer to form a wiring pattern, a multi chip module in which electrical connection is established by bumps bonded to each other through an adhesive layer, and the like.

Claims

1. A semiconductor device comprising:

a semiconductor chip;

a stud bump provided on an electrode of said semiconductor chip; and

an adhesive layer provided on a surface of said semiconductor chip on which said electrode is formed,

wherein said stud bump projects from a surface of said adhesive layer.

2. The semiconductor device according to

claim 1

, further comprising an interposer bonded through thermocompression bonding.

4. The semiconductor device according to

claim 2

, wherein said interposer is provided with a device hole.

9. The semiconductor device according to

claim 1

, wherein said adhesive layer is a thermoplastic resin with adhesion.

3. A semiconductor device comprising:

a semiconductor chip;

a protection resin layer provided on a surface of said semiconductor chip on which an electrode is formed;

a bump provided on said electrode of said semiconductor chip and exposed at a surface of said protection resin layer; and

an interposer adhered to said surface of said protection resin layer through a cured flux and electrically connected to said bump.

5. A semiconductor device comprising:

a semiconductor chip;

an adhesive layer provided on a surface of said semiconductor chip on which an electrode is formed;

a bump provided on said electrode of said semiconductor chip and exposed at a surface of said adhesive layer;

a wiring pattern adhered to said surface of said adhesive layer and partially bonded to said bump; and

an insulating and covering layer for insulating and covering said wiring pattern and selectively opening to form an external connecting portion.

6. A semiconductor device comprising:

a semiconductor chip;

a protection resin layer provided on a surface of said semiconductor chip on which an electrode is formed;

a bump provided on said electrode of said semiconductor chip and exposed at a surface of said protection resin layer;

a wiring pattern adhered to said surface of said protection resin layer through a cured flux and partially bonded to said bump; and

an insulating and covering layer for insulating and covering said wiring pattern and selectively opening to form an external connecting portion.

7. A semiconductor apparatus comprising:

two or more semiconductor devices, each of said devices including a semiconductor chip, an adhesive layer provided on a surface of said semiconductor chip on which an electrode is formed, and a bump provided on said electrode of said semiconductor chip and exposed at a surface of said adhesive layer,

wherein part of a surface of one of said semiconductor devices on which said adhesive layer is provided is adhered to part or all of a surface of another one of said semiconductor devices on which said adhesive layer is provided and they are electrically connected to each other with said bumps at the adhesion surface.

8. A semiconductor apparatus comprising:

two or more stacked semiconductor devices, each of said devices including a semiconductor chip having electrodes formed on the front and back, an adhesive layer provided on the front or back of said semiconductor chip, and a bump provided on said electrode of said semiconductor chip and exposed at a surface of said adhesive layer,

wherein one of said semiconductor devices is adhered to one of said semiconductor devices below through said adhesive layer and the electrodes thereof are connected to each other through said bump.

10. A method of manufacturing a semiconductor device, comprising the steps of:

forming a predetermined number of semiconductor chips on a semiconductor wafer and providing a bump on an electrode of each of said semiconductor chips;

forming an adhesive layer on a surface on which said bump is provided;

etching an entire surface of said adhesive layer until said bump projects; and

cutting said semiconductor wafer for division into each of said semiconductor chips.

24. The method of manufacturing a semiconductor device according to

claim 10

, wherein said adhesive layer is a thermoplastic resin with adhesion.

11. A method of manufacturing a semiconductor device, comprising the steps of:

forming a predetermined number of semiconductor chips on a semiconductor wafer and providing a bump on an electrode of each of said semiconductor chips;

forming an adhesive layer on a surface on which said bump is provided;

etching an entire surface of said adhesive layer until said bump projects;

cutting said semiconductor wafer for division into each of said semiconductor chips; and

mounting one, or two or more of said semiconductor chips on a single wiring substrate, and performing heating and pressing for adhesion to said wiring substrate with said adhesive layer and electrical connection to wiring on said wiring substrate with said bump.

12. A method of manufacturing a semiconductor device, comprising the steps of:

forming a predetermined number of semiconductor chips on a semiconductor wafer and providing a bump on an electrode of each of said semiconductor chips;

forming a protection resin layer on a surface on which said bump is provided;

etching an entire surface of said protection resin layer until said bump projects;

cutting said semiconductor wafer for division into each of said semiconductor chips;

for one, or two or more of said semiconductor chips, applying a thermosetting flux to said bump and said protection resin layer or to a wiring substrate corresponding thereto;

disposing said bump on wiring of said wiring substrate; and

performing heating to solder said bump to said wiring and cure said thermosetting flux.

13. A method of manufacturing a semiconductor device, comprising the steps of:

forming a predetermined number of semiconductor chips on a semiconductor wafer and providing a bump on an electrode of each of said semiconductor chips;

forming an adhesive layer on a surface on which said bump is provided;

etching an entire surface of said adhesive layer until said bump projects; and

bonding said semiconductor wafer to a wiring substrate through said adhesive layer and cutting said semiconductor chip along its perimeter for division into each of said semiconductor chips.

14. A method of manufacturing a semiconductor device, comprising the steps of:

forming a predetermined number of semiconductor chips on a semiconductor wafer and providing a bump on an electrode of each of said semiconductor chips;

forming an adhesive layer on a surface on which said bump is provided;

etching an entire surface of said adhesive layer until said bump projects;

aligning said semiconductor wafer with a wiring substrate through said adhesive layer, and performing heating and pressing for adhesion to said wiring substrate with said adhesive layer and electrical connection to wiring on said wiring substrate with said bump;

cutting said semiconductor chip along its perimeter for division into each of said semiconductor chips.

15. A method of manufacturing a semiconductor device, comprising the steps of:

forming a predetermined number of semiconductor chips on a semiconductor wafer and providing a bump on an electrode of each of said semiconductor chips;

forming a protection resin layer on a surface on which said bump is provided;

etching an entire surface of said protection resin layer until said bump projects;

applying a thermosetting flux to said bump and said protection resin layer or to a wiring substrate corresponding thereto;

disposing said bump on wiring of said wiring substrate;

performing heating to solder said bump to said wiring and cure said thermosetting flux; and

cutting said semiconductor chip along its perimeter for division into each of said semiconductor chips.

16. A method of manufacturing a semiconductor device, comprising the steps of:

providing a bump on an electrode of a semiconductor chip;

forming an adhesive layer on a surface on which said bump is provided;

etching an entire surface of said adhesive layer until said bump projects;

bonding said semiconductor chip to a metal foil through said adhesive layer; and

forming said metal foil into a wiring pattern.

22. The method of manufacturing a semiconductor device according to

claim 16

, further comprising the step of, after said metal foil is formed into a wiring pattern, selectively forming an insulating and covering layer on said wiring pattern.

23. The method of manufacturing a semiconductor device according to

claim 22

, further comprising the steps of, after said insulating and covering layer is selectively formed on said wiring pattern, providing a solder ball on a land portion of said wiring pattern exposed through an opening of said insulating and covering layer.

17. A method of manufacturing a semiconductor device, comprising the steps of:

providing a bump on an electrode of a semiconductor chip;

forming an adhesive layer on a surface on which said bump is provided;

etching an entire surface of said adhesive layer until said bump projects;

aligning said semiconductor chip with a metal foil through said adhesive layer, and performing heating and pressing for adhesion to said metal foil with said adhesive layer and electrical connection to said metal foil with said bump; and

forming said metal foil into a wiring pattern.

18. A method of manufacturing a semiconductor device, comprising the steps of:

providing a bump on an electrode of a semiconductor chip;

forming a protection resin layer on a surface on which said bump is provided;

etching an entire surface of said protection resin layer until said bump projects;

aligning said semiconductor chip with a metal foil through said protection resin layer;

performing heating to solder said bump to said metal foil and cure a thermosetting flux; and

forming said metal foil into a wiring pattern.

19. A method of manufacturing a semiconductor device, comprising the steps of:

forming a predetermined number of semiconductor chips on a semiconductor wafer and providing a bump on an electrode of each of said semiconductor chips;

forming an adhesive layer on a surface on which said bump is provided;

etching an entire surface of said adhesive layer until said bump projects; and

boning said semiconductor wafer to a metal foil through said adhesive layer; and

forming said metal foil into a wiring pattern; and

then, cutting said semiconductor chip along its perimeter for division into each of said semiconductor chips.

20. A method of manufacturing a semiconductor device, comprising the steps of:

forming a predetermined number of semiconductor chips on a semiconductor wafer and providing a bump on an electrode of each of said semiconductor chips;

forming an adhesive layer on a surface on which said bump is provided;

etching an entire surface of said adhesive layer until said bump projects;

aligning said semiconductor wafer with a metal foil through said adhesive layer, and performing heating and pressing for adhesion to said metal foil with said adhesive layer and electrical connection to said metal foil with said bump;

forming said metal foil into a wiring pattern; and

then, cutting said semiconductor chip along its perimeter for division into each of said semiconductor chips.

21. A method of manufacturing a semiconductor device, comprising the steps of:

forming a predetermined number of semiconductor chips on a semiconductor wafer and providing a bump on an electrode of each of said semiconductor chips;

forming a protection resin layer on a surface on which said bump is provided;

etching an entire surface of said protection resin layer until said bump projects;

aligning said semiconductor wafer with a metal foil through said protection resin layer;

performing heating to solder said bump to said metal foil and cure a thermosetting flux;

forming said metal foil into a wiring pattern; and

then, cutting said semiconductor chip along its perimeter for division into each of said semiconductor chips.

25. A semiconductor device comprising:

a semiconductor chip;

an adhesive layer provided on a surface of said semiconductor chip on which an electrode is formed;

a bump provided on said electrode of said semiconductor chip and exposed at a surface of said adhesive layer;

a tape substrate; and

an interposer,

wherein said semiconductor chip is adhered to the front of said tape substrate with said adhesive layer, said semiconductor chip is electrically connected to said tape substrate with said bump, and said interposer is connected to the back of said tape substrate for allowing electrical conduction.