Intelligent network interface system and method for accelerated protocol processing

• US 20010037397A1
• Filed: 03/09/2001
• Published: 11/01/2001
• Est. Priority Date: 10/14/1997
• Status: Active Grant

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Higgen, David A., Philbrick, Clive M., Boucher, Laurence B., Craft, Peter K., Blightman, Stephen E. J., Starr, Daryl D.
• Granted Patent: US 6,658,480 B2
• Time in Patent Office: Days
• US Class Current: 709/230
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/245 Link aggregation, e.g. trunking
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 67/62 Establishing a time schedule for servicing the requests
• CPC Class Codes: H04L 67/63 Routing a service request depending on the request content or context
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/168 specially adapted for link layer protocols, e.g. asynchronous transfer mode [ATM], synchronous optical network [SONET] or point-to-point protocol [PPP]
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04Q 2213/13093 : Personal computer, PC
• CPC Class Codes: H04Q 2213/13103 : Memory
• CPC Class Codes: H04Q 2213/13204 : Protocols
• CPC Class Codes: H04Q 2213/13299 : Bus
• CPC Class Codes: H04Q 2213/1332 : Logic circuits
• CPC Class Codes: H04Q 2213/13345 : Intelligent networks, SCP
• CPC Class Codes: H04Q 3/0029 : Provisions for intelligent networking

Abstract

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The CPD provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The CPD also assists the host CPU for those message packets that are chosen for processing by host software layers. A context for a message is defined that allows DMA controllers of the CPD to move data, free of headers, directly to or from a destination or source in the host. The context can be stored as a communication control block (CCB) that is controlled by either the CPD or by the host CPU. The CPD contains specialized hardware circuits that process media access control, network and transport layer headers of a packet received from the network, saving the host CPU from that processing for fast-path messages.

Claims

1. A system for communication between a local host and a remote host that are connectable by a network, the system comprising:

a communication processing device adapted to connect the network and the local host, said communication processing device including hardware logic configured to process network packets,

a protocol processing stack disposed in the local host and configured to create a communication control block and passing control of said communication control block to said device, with said communication control block defining a connection between the local host and the remote host,

wherein said device and said protocol processing stack are arranged such that a message transferred between the network and the local host is generally processed by said device instead of said protocol processing stack when said device owns said communication control block.

2. The system of

claim 1

, wherein said communication processing device and said protocol processing stack are arranged such that a packet transferred between the network and the local host is processed by said communication processing device instead of said protocol processing stack when said communication processing device controls said communication control block.

3. The system of

claim 1

, wherein said communication processing device is integrated into the local host.

4. The system of

claim 1

, wherein said local host contains a CPU, and said communication processing device is integrated with said CPU.

5. The system of

claim 1

, wherein the local host contains a memory controller, and said communication processing device is integrated with said memory controller.

6. The system of

claim 1

, wherein the local host contains an input/output controller, and said communication processing device is integrated with said input/output controller.

7. The system of

claim 1

, further comprising a CPU disposed in said local host, wherein said communication processing device is connected to said CPU by a host bus.

8. The system of

claim 1

, wherein said hardware logic is configured to process Transmission Control Protocol.

9. The system of

claim 1

, wherein said device is configured to compare a portion of at least one of said network packets that has been received from the network with a portion of said communication control block.

10. The system of

claim 1

, wherein said local host is configured to choose, dependent upon status generated by said communication processing device, whether to process a received packet of said network packets by said protocol processing stack, or to write data of said packet to a destination in the local host without processing said packet by said protocol processing stack.

11. An apparatus configured for communicating packets over a network, the packets having data and headers, the apparatus comprising:

a memory adapted to store a protocol processing stack,

a CPU configured to operate said protocol processing stack to process packets corresponding to a first set of protocols, and

a communication processing device adapted to connect the apparatus to the network, said communication processing device including hardware logic configured to receive the packets from the network and categorize the received packets as fast-path packets or slow-path packets, said communication processing device including a mechanism configured to transfer to said memory said slow-path packets and at least the data of said fast-path packets,

wherein said slow-path packets are processed by said CPU running said protocol processing stack, and said fast-path packets are not processed by said CPU running said protocol processing stack.

12. The apparatus of

claim 11

, wherein said communications processing device is configured to transfer to said memory a header of an initial packet of a message containing said fast-path packets, and to transfer to said memory, for subsequent fast-path packets of said message, the data of said fast-path packets without the headers.

13. The apparatus of

claim 11

, wherein said communications processing device is configured to transfer to said memory the headers and the data of said fast-path packets, and said memory is remapped, in response to a signal from said communications processing device, to provide the data without the headers of said fast-path packets to an application.

14. The apparatus of

claim 11

, wherein said communication processing device is integrated with said CPU.

15. The apparatus of

claim 11

, further comprising a memory controller, wherein said communication processing device is integrated with said memory controller.

16. The apparatus of

claim 11

, further comprising an input/output controller, wherein said communication processing device is integrated with said input/output controller.

17. The apparatus of

claim 11

, further comprising a host bus, wherein said communication processing device and said CPU are connected to said host bus.

18. The apparatus of

claim 11

, further comprising a host bus and a memory controller connected to said memory and directly connected to said host bus, wherein said communication processing device is directly connected to said host bus.

19. The apparatus of

claim 11

, wherein said hardware logic is configured to process Transmission Control Protocol.

20. The apparatus of

claim 11

, further comprising a communication control block controlled by the communication processing device and defining a connection between the apparatus and a remote host, wherein said communications processing device is configured to compare a plurality of the headers of at least one of the network packets with at least a portion of said communication control block.

22. The apparatus of

claim 20

, wherein said protocol processing stack is configured to create a communication control block defining a network, and said communication processing device references said communication control block to send said data to said destination.

23. The apparatus of

claim 20

, wherein said communications processing mechanism is configured to transfer to said memory, for processing by said protocol processing stack, a header of an initial packet of a message, and to transfer to said destination, for subsequent packets of said message, data of said subsequent packets without media access control, network or transport layer headers of said subsequent packets.

24. The apparatus of

claim 20

, wherein said communication processing device is configured to send the headers and the data of said packet to said memory, and said memory is remapped, in response to a signal from said communications processing device, to provide the data without the headers of said fast-path packets to said destination.

25. The apparatus of

claim 20

, wherein said communication processing mechanism is coupled to said CPU by a host bus.

26. The apparatus of

claim 20

, further comprising a memory controller connected to said memory, and a host bus connecting said communication processing mechanism to said memory controller.

27. The apparatus of

claim 20

, further comprising an input/output controller and a host bus, wherein said communication processing mechanism is connected to said input/output controller with said host bus.

21. An apparatus configured for communicating packets over a network, the packets having data and headers, the apparatus comprising:

a memory adapted to store a protocol processing stack,

a CPU operably coupled to said memory and configured to operate said protocol processing stack to process packets corresponding to a first set of protocols,

a communication processing device including hardware logic configured to categorize media access control, network and transport layer headers of a packet received from the network, and create a status of said packet, said communication processing device including a comparison mechanism operably coupled to said hardware logic and adapted to reference said status to determine whether to send said packet to said memory for processing by said CPU running said protocol processing stack, or to send at least the data of said packet to said memory, with the data of said packet mapped to a destination in said memory without processing of said media access control, network or transport layer headers by said CPU running said protocol processing stack.