Method and circuitry for supplying clock to internal circuit
First Claim
1. A method of supplying a system clock signal to an internal circuit, comprising the steps of:
- when returning to a clock supply state in which a phase-locked loop or PLL frequency multiplier is generating a frequency-multiplied clock signal from an input clock signal and supplying the frequency-multiplied clock signal to said internal circuit, the frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of the input clock signal, from a clock supply stopping state in which said PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal, determining whether the frequency-multiplied clock signal from said PLL frequency multiplier becomes stable; and
supplying the frequency-multiplied clock signal as the system clock signal to said internal circuit after it is determined that the frequency-multiplied clock signal becomes stable.
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Accused Products
Abstract
Clock supply circuitry comprises a phase-locked loop or PLL frequency multiplier for generating a frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of an input clock signal. The clock supply circuitry further includes a PLL output stability detecting circuit. When the clock supply circuitry is made to return from a clock supply stopping state in which the PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal to a clock supply state in which the PLL frequency multiplier is generating and supplying the frequency-multiplied clock signal to an internal circuit, the PLL output stability detecting circuit determines whether the frequency-multiplied clock signal from the PLL frequency multiplier becomes stable. After the PLL output stability detecting circuit determines that the frequency-multiplied clock signal becomes stable, it supplies the frequency-multiplied clock signal from the PLL frequency multiplier as a system clock signal to the internal circuit.
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Citations
6 Claims
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1. A method of supplying a system clock signal to an internal circuit, comprising the steps of:
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when returning to a clock supply state in which a phase-locked loop or PLL frequency multiplier is generating a frequency-multiplied clock signal from an input clock signal and supplying the frequency-multiplied clock signal to said internal circuit, the frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of the input clock signal, from a clock supply stopping state in which said PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal, determining whether the frequency-multiplied clock signal from said PLL frequency multiplier becomes stable; and
supplying the frequency-multiplied clock signal as the system clock signal to said internal circuit after it is determined that the frequency-multiplied clock signal becomes stable. - View Dependent Claims (2)
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3. Clock supply circuitry for supplying a system clock signal to an internal circuit, said circuitry comprising:
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a phase-locked loop or PLL frequency multiplier for generating a frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of an input clock signal; and
a PLL output stability detecting circuit for determining whether the frequency-multiplied clock signal from said PLL frequency multiplier becomes stable when said clock supply circuitry is made to return from a clock supply stopping state in which said PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal to a clock supply state in which said PLL frequency multiplier is generating and supplying the frequency-multiplied clock signal to said internal circuit, and for supplying the frequency-multiplied clock signal from said PLL frequency multiplier as the system clock signal to said internal circuit after said PLL output stability detecting circuit determines that the frequency-multiplied clock signal becomes stable. - View Dependent Claims (4, 5, 6)
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Specification