DISPLAY SYSTEM WITH MULTIPLEXED PIXELS

• US 20010040538A1
• Filed: 08/05/1999
• Published: 11/15/2001
• Est. Priority Date: 05/13/1999
• Status: Abandoned Application

• Current Assignee: Snap, Inc.
• Original Assignee: Snap, Inc.
• Inventors: QUANRUD, WILLIAM A.
• Application Number:
  US09/369,685
• Publication Number:
  US 20010040538A1
• Time in Patent Office: Days
• US Class Current: 345/55
• CPC Class Codes: G02F 1/136 Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit G02F1/135 takes precedence
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2025 the sub-frames having all the same time duration
• CPC Class Codes: G09G 3/2033 with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/34 by control of light from an independent source
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 5/022 using memory planes
• CPC Class Codes: G09G 5/34 for rolling or scrolling

Abstract

A display matrix is provided comprising a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel and at least partially positioned outside of a footprint of the pixel, the display circuit including a plurality of memory cells, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time.

Claims

1. A display matrix comprising:

a plurality of display elements, each display element including

a pixel, and

a display circuit electrically connected to the pixel and at least partially positioned outside of a footprint of the pixel, the display circuit including

a plurality of memory cells, and

a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time.

2. The display matrix according to

claim 1

, wherein the plurality of memory cells includes at least 2 memory cells.

3. The display matrix according to

claim 1

, wherein the plurality of memory cells includes at least 3 memory cells.

4. The display matrix according to

claim 1

, wherein the plurality of memory cells includes between 2 and 9 memory cells.

5. The display matrix according to

claim 1

, wherein the plurality of memory cells includes at least 9 memory cells.

6. The display matrix according to

claim 1

, wherein the memory cells are static random access memory (SRAM) cells.

7. The display matrix according to

claim 1

, wherein a first display element has a display circuit of second display element at least partially positioned inside the footprint of the pixel of the first display element.

8. The display matrix according to

claim 1

, further including a data line electronically connected to both a first display circuit of a first display element and a second display circuit of a second display element, the data line enabling reading from and writing to the first and second display circuits.

9. The display matrix according to

claim 1

, further including two or more data lines, each data line electronically connected to both a first display circuit of a first display element and a second display circuit of a second display element, the data line enabling reading from and writing to the first and second display circuits.

10. The display matrix of

claim 9

, wherein the two or more data lines comprise a first data line which carries a bit signal, and a second data line which carries a bit bar signal.

11. A display matrix comprising:

a first display element including

a first pixel, and

a first display circuit including a plurality of memory cells electrically connected to the first pixel;

a second display element including

a second pixel, and

a second display circuit including a plurality of memory cells electrically connected to the second pixel, the second display circuit being at least partially positioned within a footprint of the second pixel and within a footprint of the first pixel.

12. The display according to

claim 11

, wherein the first display circuit is at least partially positioned within the footprint of the second pixel.

13. The display matrix according to

claim 12

, further including a set of data lines is electronically connected to the first display circuit and the second display circuit, the set of data lines enabling reading to and writing from the first display circuit and the second display circuit.

14. A virtual image display system comprising:

a display matrix including a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel and at least partially positioned outside of a footprint of the pixel, the display circuit including a plurality of memory cells, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time;

peripheral control circuits for controlling read and write operations to the memory cells; and

one or more magnification optics for magnifying the sub-images formed by the display matrix.

15. The virtual image display system according to

claim 14

, further including a light emitting mechanism provided at each pixel.

16. The virtual image display system according to

claim 14

, further including a light modulating mechanism provided at each pixel.

17. The virtual image display system according to

claim 16

, further including an illumination source for illuminating the pixels.

18. The display system according to

claim 16

, wherein the light modulating mechanism is a liquid crystal material.

19. A virtual image display system comprising:

a display matrix comprising a first display element including a first pixel, and a first display circuit including a plurality of memory cells electrically connected to the first pixel, a second display element including a second pixel, and a second display circuit including a plurality of memory cells electrically connected to the second pixel, the second display circuit being at least partially positioned within a footprint of the second pixel and within a footprint of the first pixel;

peripheral control circuits for controlling read and write operations to the memory cells; and

one or more magnification optics for magnifying the sub-images formed by the display matrix.

20. The virtual image display system of

claim 19

, wherein the first pixel is partially within the footprint of the second pixel.

21. The virtual image display system of

claim 19

, wherein a set of data lines is connected to the first display circuit and the second display circuit, the set of data lines enabling reading to and writing from the first and second display circuits.

22. The virtual image display system according to

claim 19

, wherein the display system is a display component of a device selected from the group consisting of portable computers, personal communicators, personal digital assistants, modems, pagers, video and camera viewfinders, mobile phones, and television monitors.

23. A method for reducing the number of address lines in a pixel-based display system, the method comprisng:

electrically connecting a plurality of display circuits to a plurality of pixels each having a footprint, the plurality of display circuits controlling the operation of the plurality of pixels;

positioning the plurality of display circuits relative to the plurality of pixels such that at least a portion of the plurality of display circuits are not entirely positioned within the footprint of a single pixel; and

connecting data lines to the plurality of data circuits to read and write data to the plurality of data circuits.

24. The method according to

claim 23

, wherein at least a portion of the plurality of data circuits includes at least 2 memory cells per data circuit.

25. The method according to

claim 23

, wherein at least a portion of the plurality of data circuits includes at least 3 memory cells per data circuit.

26. The method according to

claim 23

, wherein at least a portion of the plurality of data circuits includes at least 9 memory cells per data circuit.

27. The method according to

claim 23

, wherein at least a portion of the plurality of data circuits includes between 2 and 9 memory cells per data circuit.

28. The method according to

claim 23

, wherein positioning the plurality of display circuits includes positioning at least a portion of the plurality of display circuits within the footprint of at least two pixels.

29. The method according to

claim 23

, wherein positioning the plurality of display circuits includes positioning at least a portion of the plurality of display circuits within the footprint of at least three pixels.