CMOS sensor array with a memory interface

• US 20010040631A1
• Filed: 01/03/2001
• Published: 11/15/2001
• Est. Priority Date: 05/09/2000
• Status: Active Grant

• Current Assignee: Pixim, Inc. (Sony Group Corp.)
• Original Assignee: Pixim, Inc. (Sony Group Corp.)
• Inventors: Yang, David Xiao Dong, Ewedemi, Odutola Oluseye, Deng, Zhonghan John, Motta, Ricardo Jansson
• Granted Patent: US 6,985,181 B2
• Time in Patent Office: Days
• US Class Current: 348/294
• CPC Class Codes: H04N 1/00307 with a mobile telephone apparatus constructional features of portable telephone sets H04M1/0202; mobile radio systems H04W84/00
• CPC Class Codes: H04N 2201/0068 Converting from still picture data
• CPC Class Codes: H04N 23/665 involving internal camera communication with the image sensor, e.g. synchronising or multiplexing SSIS control signals
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 7/142 Constructional details of the terminal equipment, e.g. arrangements of the camera and the display

Abstract

An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.

Claims

1. An image sensor, comprising:

a sensor array, including a two-dimensional array of pixel elements, that outputs digital signals as pixel data representing an image of a scene;

a data memory coupled to said sensor array and fabricated with said sensor array on a same integrated chip, said data memory for storing said digital pixel data; and

a logic circuit coupled to said data memory and fabricated with said data memory on said same integrated chip, said logic circuit providing a memory interface for exporting said pixel data.

2. The image sensor of

claim 1

, wherein said memory interface is a SRAM interface.

3. The image sensor of

claim 1

, wherein said memory interface is a DRAM interface.

4. The image sensor of

claim 1

, wherein said memory interface is a packet protocol synchronous DRAM interface.

5. An image sensor, comprising:

a pixel array, including a two-dimensional array of pixel elements, that outputs analog signals as pixel data representing an image of a scene;

an analog-to-digital converter coupled to said pixel array for converting said analog signals into digital pixel data;

a data memory coupled to said analog-to-digital converter and fabricated with said pixel array and said analog-to-digital converter on a same integrated chip, said data memory for storing said pixel data; and

a logic circuit coupled to said data memory and fabricated with said data memory on said same integrated chip, said logic circuit providing a memory interface for exporting said pixel data.

6. The image sensor of

claim 5

, wherein said memory interface is a SRAM interface.

7. The image sensor of

claim 5

, wherein said memory interface is a DRAM interface.

8. The image sensor of

claim 5

, wherein said memory interface is a packet protocol synchronous DRAM interface.

9. An image sensor, comprising:

a pixel array, including a two-dimensional array of pixel elements, that outputs analog signals as pixel data representing an image of a scene;

a data memory coupled to said pixel array and fabricated with said pixel array on a same integrated chip, said data memory for storing said pixel data; and

a logic circuit coupled to said data memory and fabricated with said data memory on said same integrated chip, said logic circuit providing a memory interface for exporting said pixel data.

10. The image sensor of

claim 9

, wherein said memory interface is a SRAM interface.

11. The image sensor of

claim 9

, wherein said memory interface is a DRAM interface.

12. The image sensor of

claim 9

, wherein said memory interface is a packet protocol synchronous DRAM interface.

13. An image sensor, comprising:

a sensor array, including a two-dimensional array of pixel elements, that outputs digital signals as pixel data representing an image of a scene; and

a dual-port data memory, a first port of said dual-port data memory coupled to said sensor array for storing said pixel data, and a second port of said dual-port data memory providing a memory interface for exporting said pixel data, said dual-port data memory being fabricated with said sensor array on a same integrated chip.

14. An imaging system, comprising:

an image sensor, comprising;

a sensor array, including a two-dimensional array of pixel elements, that outputs digital signals as pixel data representing an image of a scene;

a data memory coupled to said sensor array and fabricated with said sensor array on a same integrated chip, said data memory for storing said pixel data;

a logic circuit coupled to said data memory and fabricated with said data memory on said same integrated chip, said logic circuit providing a memory interface for exporting said pixel data; and

an image processing device including a memory interface port;

wherein said image sensor is coupled to said memory interface port of said image processing device and said image processing device accesses pixel data in said image sensor using a memory interface protocol.

15. The image sensor of

claim 14

, wherein said memory interface of said image sensor is a SRAM interface.

16. The image sensor of

claim 14

, wherein said memory interface of said image sensor is a DRAM interface.

17. The image sensor of

claim 14

, wherein said memory interface of said image sensor is a packet protocol synchronous DRAM interface.

18. A method in an image sensor, comprising:

capturing an image of a scene using a sensor array;

storing pixel data representative of said images in a data memory being fabricated on a same integrated circuit as said sensor array; and

outputting said pixel data to an image processing device using a memory interface protocol.

19. The image sensor of

claim 18

, wherein said memory interface protocol is a SRAM interface protocol.

20. The image sensor of

claim 18

, wherein said memory interface protocol is a DRAM interface protocol.

21. The image sensor of

claim 18

, wherein said memory interface protocol is a packet protocol synchronous DRAM interface protocol.