Manufacturing method of a liquid crystal display

• US 20010040649A1
• Filed: 06/07/2001
• Published: 11/15/2001
• Est. Priority Date: 03/16/1999
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Fujitsu Limited
• Inventors: Ozaki, Kiyoshi
• Granted Patent: US 6,469,769 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

It is intended to provide a manufacturing method of a liquid crystal display that can reduce the manufacturing cost by decreasing the number of masks. A gate insulating film, a semiconductor film, and a silicon nitride film are laid on a substrate on which a gate bus line is formed, back exposure is performed by using the gate bus line as a mask, and the silicon nitride film is then patterned, whereby a channel protective film is formed along the gate bus line. Two device isolation holes are formed over the gate bus line at two locations that are on both sides of a source electrode and a drain electrode and that are separated from each other in the extending direction of the gate bus line. A thin-film transistor is formed in such a manner that a semiconductor active film is formed by a portion of the semiconductor film that is interposed between the two device isolation holes and is thereby electrically isolated from other pixel regions and that a gate electrode is formed by a portion of the gate bus line that is located between the two device isolation holes.

Claims

1. A manufacturing method of a liquid crystal display, comprising the steps of:

forming a gate insulating film, a semiconductor film, and a first insulating film in this order on a substrate and gate bus lines that are formed on the substrate;

forming channel protective films extending along the respective gate bus lines by performing back exposure using the gate bus lines as a mask and then patterning the first insulating film;

forming, for each pixel region, on the associated channel protective film, a source electrode and a drain electrode that are opposed to each other; and

forming, by etching away at least the associated channel protective film and the semiconductor film, two device isolation holes over the associated gate bus line at two locations that are on both sides of the source electrode and the drain electrode.

2. The manufacturing method according to

claim 1

, further comprising the steps of:

forming storage capacitor lines at the same as the gate bus lines are formed;

forming protective films extending along the respective storage capacitor lines by performing back exposure using the storage capacitor lines as a mask and then patterning the first insulating film;

forming storage capacitor electrodes over the respective storage capacitor lines with the protective film interposed in between; and

forming, by etching away at least the protective film and the semiconductor film, two device isolation holes in the pixel region at two locations that are separated from each other in an extending direction of the associated storage capacitor line, whereby a storage capacitor portion is formed between the two device isolation holes so as to be isolated electrically from the other pixel regions.

3. The manufacturing method according to

claim 2

, further comprising the step of forming device isolation holes in the vicinity of terminal portions of the respective gate bus lines or terminal portions of the respective storage capacitor lines.