Graded thin films

• US 20010041250A1
• Filed: 03/06/2001
• Published: 11/15/2001
• Est. Priority Date: 03/07/2000
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM Microchemistry Oy (ASM International NV)
• Inventors: Raaijmakers, Ivo, Haukka, Suvi P., Werkhoven, Christian J.
• Granted Patent: US 6,534,395 B2
• Time in Patent Office: Days
• US Class Current: 428/212
• CPC Class Codes: C23C 16/029 Graded interfaces
• CPC Class Codes: C23C 16/34 Nitrides C23C16/303 takes precedence
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: C23C 16/403 of aluminium, magnesium or beryllium
• CPC Class Codes: C23C 16/405 of refractory metals or yttrium
• CPC Class Codes: C23C 16/452 by activating reactive gas streams before their introduction into the reaction chamber, e.g. by ionisation or addition of reactive species
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: C23C 16/45531 specially adapted for making ternary or higher compositions
• CPC Class Codes: C23C 16/45534 Use of auxiliary reactants other than used for contributing to the composition of the main film, e.g. catalysts, activators or scavengers
• CPC Class Codes: C30B 25/14 Feed and outlet means for the gases; Modifying the flow of the reactive gases
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28562 : Selective deposition
• CPC Class Codes: H01L 21/3141 : Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3145 : formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/31612 : on a silicon body
• CPC Class Codes: H01L 21/3162 : on a silicon body
• CPC Class Codes: H01L 21/31641 : Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/3185 : of siliconnitrides
• CPC Class Codes: H01L 21/76846 : Layer combinations
• CPC Class Codes: H01L 21/76873 : for electroplating
• CPC Class Codes: H01L 21/76879 : by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2221/1089 : Stacks of seed layers
• CPC Class Codes: H01L 29/4908 : for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 428/24942 : including components having same physical characteristic in differing degree
• CPC Class Codes: Y10T 428/2495 : Thickness [relative or absolute]

Abstract

Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO₂) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a graded transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Claims

1. A method of forming a thin film with a varying composition in an integrated circuit comprising:

placing a substrate in a reaction chamber;

introducing first and second vapor phase reactants in alternate and temporally separated pulses to the substrate in a plurality of deposition cycles; and

introducing varying amounts of a third vapor phase reactant to the substrate during said plurality of deposition cycles.

2. The method of

claim 1

, wherein the first vapor phase reactant comprises a silicon source gas.

3. The method of

claim 2

, wherein the silicon source gas is selected from the group consisting of silanes of the formula Si_mL_2m+2, siloxanes of the formula Si_yO_y−

1L_2y+2, and silazanes of the formula Si_y(NH)<sub>y−

1</sub>L_2y+2, where m and y are integers and L is a ligand.

4. The method of

claim 3

, wherein the ligands in the silicon source gas are selected from the group consisting of H, F, Cl, Br, I, alkyl, aryl, alkoxy, vinyl, cyano, isocyanato, amino, silyl, alkylsilyl, alkoxysilyl, silylene and alkylsiloxane groups

5. The method of

claim 3

, wherein the second vapor phase reactant comprises an oxidant source gas and the third vapor phase reactant comprises a nitrogen source gas.

6. The method of

claim 5

, wherein the oxidant source gas comprises water vapor and the nitrogen source gas comprises ammonia.

7. The method of

claim 1

, wherein the first vapor phase reactant comprises a first metal source gas.

8. The method of

claim 7

, wherein the second vapor phase reactant is an oxidant and the third vapor phase reactant comprises a second metal source gas different from the first metal source gas.

9. The method of

claim 8

, wherein the first and second vapor phase reactants produce an interface layer for a gate dielectric, and the third vapor phase reactant produces a higher dielectric constant material.

10. The method of

claim 9

, wherein the interface layer comprises aluminum oxide.

11. The method of

claim 10

, wherein the higher dielectric constant material comprises zirconium oxide.

12. The method of

claim 1

, wherein the first vapor phase reactant is a first metal source gas, the second vapor phase reactant is a nitrogen source gas, and the third vapor phase reactant is a second metal source gas.

13. The method of

claim 12

, wherein the thin film comprises a graded transition layer between a metal nitride barrier layer and a more conductive material.

14. The method of

claim 12

, wherein the third vapor phase reactant is a copper source gas.

15. The method of

claim 14

, wherein the thin film forms a graded transition layer between a metal nitride barrier layer and a copper fill in a damascene trench.

16. The method of

claim 15

, wherein introducing comprises adding progressively more copper source gas to the deposition cycles.

17. The method of

claim 16

, wherein introducing varying amounts of the third vapor phase reactant comprises providing copper source gas pulses to the deposition cycles with greater frequency as the deposition proceeds.

18. The method of

claim 14

, wherein introducing varying amounts of the third vapor phase reactant comprises varying a copper concentration from a lower surface of the transition layer to an upper surface of the transition layer.

19. The method of

claim 18

, wherein the copper concentration is lowest at the lower surface and highest at the upper surface.

20. The method of

claim 19

, wherein introducing varying amounts of the third vapor phase reactant comprises linearly grading the copper concentration from the lower surface to the upper surface.

21. The method of

claim 19

, wherein introducing varying amounts of the third vapor phase reactant comprises providing 0% copper at the lower surface and about 50% copper at the upper surface.

22. The method of

claim 19

, wherein introducing varying amounts of the third vapor phase reactant comprises forming a pure metal nitride at the lower surface and a pure copper layer at the upper surface

23. The method of

claim 19

, forming the graded transition layer with a thickness of less than 50 Å

.

24. The method of

claim 19

, forming the graded transition layer with a thickness of about 10 Å

.

25. The method of

claim 1

, wherein introducing varying amounts of the third vapor phase reactant comprises providing pulses of the third vapor phase reactant to the deposition cycles with varying frequency as the deposition proceeds.

26. The method of

claim 25

, wherein introducing varying amounts of the third vapor phase reactant comprises providing pulses of the third vapor phase reactant to the deposition cycles with greater frequency as the deposition proceeds.

27. The method of

claim 25

, wherein introducing varying amounts of the third vapor phase reactant comprises providing pulses of the third vapor phase reactant to the deposition cycles with lesser frequency as the deposition proceeds.

28. The method of

claim 1

, wherein introducing varying amounts of the third vapor phase reactant comprises providing varying levels of the third vapor phase reactant in each of the deposition cycles as the deposition proceeds.

29. The method of

claim 28

, wherein the varying levels of the third vapor phase reactant are provided simultaneously with the second vapor phase reactant in each cycle.

30. The method of

claim 28

, wherein the varying levels of the third vapor phase reactant are provided in separate pulses of varying duration.

31. The method of

claim 28

, wherein the varying levels of the third vapor phase reactant replace atoms at the surface of the thin film from a previous pulse.

32. The method of

claim 1

, forming a graded thin film with a thickness of less than about 50 Å

.

33. The method of

claim 32

, wherein introducing varying amounts of the third vapor phase reactant comprises linearly varying an amount of an impurity incorporated into the layer during the deposition.

34. A thin film in an integrated circuit having a thickness of less than 100 Å

defined between an upper surface and a lower surface, said thin film having a controlled and varying composition between the upper surface and the lower surface.

35. The thin film of

claim 34

, wherein the thickness is less than about 7 Å

and 80 Å

.

36. The thin film of

claim 35

, wherein the thickness is less than 50 Å

.

37. The thin film of

claim 36

, wherein said varying composition comprises a graded concentration of an impurity.

38. The thin film of

claim 37

, wherein the concentration of the impurity is less than about 0.1% at the lower surface.

39. The thin film of

claim 38

, wherein the concentration of the impurity is about 0% at the lower surface.

40. The thin film of

claim 37

, wherein the concentration of the impurity is greater than about 5% at the upper surface.

41. The thin film of

claim 40

, wherein the concentration of the impurity is greater than about 10% at the upper surface.

42. The thin film of

claim 34

, forming a transistor gate dielectric.

43. The thin film of

claim 42

, demonstrating an equivalent oxide thickness of less than about 2.0 nm.

44. The thin film of

claim 43

, demonstrating an equivalent oxide thickness of less than about 1.7 nm.

45. The thin film of

claim 42

, comprising at least one molecular monolayer of silicon oxide at the lower surface.

46. The thin film of

claim 45

, comprising at least one molecular monolayer of silicon nitride at the upper surface.

47. The thin film of

claim 42

, comprising aluminum oxide at one of the upper and lower surfaces, and a higher dielectric constant material adjacent thereto.

48. The thin film of

claim 47

, wherein the aluminum oxide is formed at the lower surface directly adjacent to a semiconductor substrate, the aluminum oxide being graded with the higher dielectric constant material.

49. The thin film of

claim 48

, wherein the higher dielectric constant material comprises zirconium oxide.

50. The thin film of

claim 34

, wherein said varying composition comprises a varying nitrogen concentration from the lower surface to the upper surface.

51. The thin film of

claim 50

, wherein the nitrogen concentration is progressively varied from a lowest concentration at the lower surface and a highest concentration at the upper surface.

52. The thin film of

claim 51

, comprising a linearly graded nitrogen concentration from the lower surface to the upper surface

53. The thin film of

claim 52

, wherein the nitrogen concentration is less than about 0.1% at the lower surface and greater than about 5% at the upper surface.

54. The thin film of

claim 53

, comprising substantially pure silicon dioxide at the lower surface and substantially pure silicon nitride at the upper surface.

55. The thin film of

claim 34

, wherein said varying composition comprises an increasing copper concentration from the lower surface to the upper surface.

56. The thin film of

claim 55

, wherein said varying composition comprises a decreasing metal nitride concentration from the lower surface to the upper surface.

57. The thin film of

claim 56

, having a thickness between about 7 Å

and 80 Å

.

58. A method of forming an integrated circuit, comprising depositing a layer having a graded concentration of an impurity from a lower surface to an upper surface by exposing a substrate to alternating surface reactions of vapor-phase reactants.