Partially removable spacer with salicide formation

• US 20010041398A1
• Filed: 01/30/2001
• Published: 11/15/2001
• Est. Priority Date: 04/20/1999
• Status: Abandoned Application

• Current Assignee: Paul D. Angello, Peter Smeys, Scott W. Crowder
• Original Assignee: Paul D. Angello, Peter Smeys, Scott W. Crowder
• Inventors: Angello, Paul D., Smeys, Peter, Crowder, Scott W.
• Application Number:
  US09/771,697
• Publication Number:
  US 20010041398A1
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer

Abstract

Formation of sidewalls on a gate structure in layers having a differential etch rate for certain etchants allows metallization and salicide formation annealing of a gate electrode and source/drain regions prior to shallow impurity implantation and impurity activation annealing at the location of a removable portion of a sidewall spacer establishing a gap between source/drain regions and remaining sidewalls of a gate structure. Therefore, diffusion of impurities to a greater depth and impurity deactivation during salacide formation annealing is avoided in a high performance semiconductor device such as a field effect transistor of extremely small dimensions.

Claims

1. A method of semiconductor device fabrication including the steps of

forming a composite sidewall on lateral sides of a polysilicon gate structure on a dielectric layer on a substrate,

performing self-aligned silicidation on said polysilicon gate structure and said substrate exposed by patterning of said dielectric layer,

partially removing said composite sidewall to expose a further area of said substrate, and

implanting impurities in said further area of said substrate.

2. A method as recited in

claim 1

, wherein said step of forming a composite sidewall includes the steps of

forming a layer of nitride, and

forming a layer of oxide over said layer of nitride.

3. A method as recited in

claim 1

, wherein said step of forming a composite sidewall includes the steps of

forming a layer of oxide of a first density, and

forming a layer of oxide of a second density over said layer of oxide of said first density.

4. A method as recited in

claim 1

, wherein said step of forming a composite sidewall includes the steps of

forming a layer of oxide,

forming a layer of nitride over said layer of oxide, and

forming a second layer of oxide over said layer of nitride.

5. A semiconductor device comprising

a gate structure,

source/drain regions in a semiconductor layer separated from said gate structure by a gap, and

an implanted region in said gap between a silicided source/drain region and a sidewall on a silicided gate structure.

6. A semiconductor device as recited in

claim 5

, wherein said gate structure includes a sidewall defining said gap.

7. A semiconductor device as recited in

claim 6

, wherein said sidewall comprises a layer of oxide.

8. A semiconductor device as recited in

claim 6

, wherein said sidewall comprises a layer of nitride.

9. A semiconductor device as recited in

claim 6

, wherein said sidewall comprises a layer of oxide covered by a layer of nitride.

10. A semiconductor device as recited in

claim 5

, wherein a surface of a gate polysilicon portion of said gate structure and said source/drain region include a silicide layer.

11. A semiconductor device as recited in

claim 5

, further including a diffused region extending from said implanted region under said gate structure.

12. A semiconductor device formed by a method comprising the steps of

forming a composite sidewall on lateral sides of a polysilicon gate structure on a dielectric layer on a substrate,

performing self-aligned silicidation on said polysilicon gate structure and said substrate exposed by patterning of said dielectric layer,

partially removing said composite sidewall to expose a further area of said substrate, and

implanting impurities in said further area of said substrate.

13. A method as recited in

claim 12

, wherein said step of forming a composite sidewall includes the steps of

forming a layer of nitride, and

forming a layer of oxide over said layer of nitride.

14. A method as recited in

claim 12

, wherein said step of forming a composite sidewall includes the steps of

forming a layer of oxide of a first density, and

forming a layer of oxide of a second density over said layer of oxide of said first density.

15. A method as recited in

claim 12

, wherein said step of forming a composite sidewall includes the steps of

forming a layer of oxide,

forming a layer of nitride over said layer of oxide, and

forming a second layer of oxide over said layer of nitride.