Angle implant process for cellular deep trench sidewall doping

• US 20010041400A1
• Filed: 05/10/2001
• Published: 11/15/2001
• Est. Priority Date: 05/15/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ren, Lipping, Sridevan, Srikant
• Granted Patent: US 6,509,240 B2
• Time in Patent Office: Days
• US Class Current: 438/200
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A process is described for making a superjunction semiconductor device. a large number of symmetrically spaced trenches penetrate the N⁻ epitaxial layer of silicon atop an N⁺ body to a depth of 35 to 40 microns. The wells have a circular cross-section and a diameter of about 9 microns. The trench walls are implanted by an ion implant beam of boron which is at a slight angle to the axis of the trenches. The wafer is intermittently or continuously rotated about an axis less than 90° to its surface to cause skewing of the implant beam and more uniform distribution of boron ions over the interior surfaces of the trenches.

Claims

1. The process of manufacture of a superjunction device comprising the steps of forming spaced parallel trenches into a silicon wafer of one conductivity type;

each of said trenches being perpendicular to the top surface of said silicon wafer;

each of said trenches having approximately the same depth and cross-section;

directing an implant beam of a species which defines a second conductivity type toward the surface of said silicon wafer and at an angle to the axes of each of said trenches;

said angle being sufficiently small that the full length of the interior surface of each of said cells receives implanted ions from said implant source; and

rotating said wafer to expose the full surface area of the interior of each of said trenches to the implant beam.

2. The process of

claim 1

, wherein said trenches are symmetrically disposed over the surface of said wafer.

3. The process of

claim 1

, wherein said ion implant angle is between 1 degrees and 20 degrees.

4. The device of

claim 1

, wherein said one conductivity type is the N type.

5. The process of

claim 2

, wherein said ion implant angle is between 1 degrees and 20 degrees.

6. The device of

claim 1

, wherein said trenches have a depth of greater than about 25 microns and a width which is less than about 9 microns.