Trench-gate semiconductor devices

• US 20010041407A1
• Filed: 05/11/2001
• Published: 11/15/2001
• Est. Priority Date: 05/13/2000
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Brown, Adam R.
• Granted Patent: US 6,586,800 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A trench-gate MOSFET or ACCUFET has its gate (21) in a first trench (20) that extends through a channel-accommodating body region (15) to a drain region (14). Within the transistor cells, a second trench (40) comprising deposited highly-doped semiconductor material (41) extends to the drain region (14). This highly-doped material (41) is of opposite conductivity type to the drain region (14) and, together with a possible out-diffusion profile (42), forms a localized region (41, 42) that is separated from the first trench (20) by the body region 15. A source electrode (23) contacts the source region (13) and the whole top area of the localized region (41, 42). In a MOSFET, the localized region (41, 42) provides protection against turning on of the cell'"'"'s parasitic bipolar transistor. In an ACCUFET (FIG. 9), the localized region (41, 42) depletes the channel-accommodating body region (15A). In both devices the localized region (41, 42) is well-defined and can be narrow to enable a small transistor cell size. Furthermore, before filling the second trench (40) with its semiconductor material (41), the drain region (14) can be readily provided with an avalanche-breakdown region (64) at the bottom of the second trench (40), for example by implanting dopant ions (60) of the same conductivity type as the drain region (14). This avalanche-breakdown region (64) improves the ruggedness of the device. It can also aid current spreading (66) in the drain region (14) in the conductive state of the transistor.

Claims

1. A trench-gate semiconductor device comprising a semiconductor body having a plurality of transistor cells, wherein each transistor cell is surrounded by a trench-gate comprising a first trench extending into the semiconductor body with gate material in the trench, an insulating overlayer on top of the gate material, a source region of a first conductivity type adjacent to the trench-gate, a channel-accommodating body region adjacent to the trench-gate under the source region, and a drain region of the first conductivity type adjacent to the trench-gate under the channel-accommodating body region, wherein at least some of the transistor cells have a localised region of a second conductivity type, opposite to the first conductivity type, which is of higher conductivity than the channel-accommodating region, the localised region extending into the semiconductor body to the drain region and being separated from the trench-gate first trench by the channel-accommodating body region, wherein a source electrode extends over said insulating overlayer and contacts the source region and the localised region, and wherein the device is characterised in that each said localised region comprises deposited semiconductor material of the second conductivity type which fills a second trench extending into the semiconductor body, with the source electrode contacting said localised region on the whole top area of the second trench.

2. A device as claimed in

claim 1

, wherein every one of said plurality of transistor cells has a said localised region.

3. A device as claimed in

claim 1

or

claim 2

, wherein there is an insulating layer in each said first trench between the gate material in the first trench and the semiconductor body adjacent the first trench.

4. A device as claimed in any one of

claims 1

to

3

, wherein the channel-accommodating body region in each transistor cell is of the second conductivity type.

5. A device as claim in any one of

claims 1

to

3

, wherein the channel-accommodating body region in each transistor cell is of the first conductivity type.

6. A device as claimed in

claim 5

, wherein the channel-accommodating body region in each transistor cell is integral with said drain region.

7. A device as claimed in any one of the preceding claims, wherein, in each transistor cell having a said localised region, said source region extends laterally from said first trench to adjacent said localised region.

8. A device as claimed in any one of the preceding claims, wherein said deposited semiconductor material of each said localised region is doped polycrystalline silicon of said second conductivity type.

9. A device as claimed in

claim 8

, wherein said gate material in said first trench of each transistor cell is doped polycrystalline silicon of said first conductivity type.

10. A device as claimed in any one of

claims 1

to

9

, wherein each said second trench extends deeper into the drain region than the first trench surrounding that second trench.

11. A device as claimed in any one of

claims 1

to

9

, wherein each said second trench extends the same depth into the drain region as the first trench surrounding that second trench.

12. A device as claimed in any one of the preceding claims, wherein each said localised region includes an out-diffused region extending from the side and bottom of the respective second trench, the out-diffused region having a diffusion profile of dopant from the deposited semiconductor material which fills the respective second trench.

13. A device as claimed in any one of the preceding claims, wherein the drain region comprises an avalanche-breakdown region of the first conductivity type that forms a p-n junction with the localised region at the bottom of the second trench and that has a higher doping concentration than the adjacent portion of the drain region so as to determine an avalanche breakdown voltage for the p-n junction.

14. A device as claimed in

claim 13

, wherein the location of the avalanche-breakdown region is deeper in the drain region than the depth of the first trench that provides the trench-gate so as to aid current spreading in the drain region.

15. A method of manufacturing a semiconductor device as claimed in any one of

claims 1

to

9

, wherein the method includes the steps of:

(a) simultaneously forming all of said first trenches and afterwards providing said gate material in said first trenches; and

then later

(b) simultaneously forming all of said second trenches and afterwards filling said second trenches with said deposited semiconductor material of the second conductivity type.

16. A method as claimed in

claim 15

, wherein a layer of insulating material is provided on the semiconductor body and on the gate material after step (a), and windows are then provided in the insulating material, the formation of said second trenches as in step (b) is performed by etching through said windows, said windows are enlarged after step (b) to expose said source regions while leaving the insulating material to provide said insulating overlayers on top of the gate material, and then said source electrode is provided in said enlarged windows and on said insulating overlayers.

17. A method of manufacturing a semiconductor device as claimed in any one of

claims 1

to

9

, wherein the method includes the steps of:

(a) simultaneously forming all of said first and second trenches;

(b) providing said gate material in said first trenches; and

(c) filling said second trenches with said deposited semiconductor material of the second conductivity type.

18. A method as claimed in

claim 16

, wherein the step (b) is performed before step (c).

19. A method as claimed in

claim 18

, wherein the first and second trenches are filled with insulating material after step (a), a mask is provided over the semiconductor body and insulating material filled second trenches, said first mask having first windows at the insulating material filled first trenches, said insulating material is removed from the first trenches using said first windows, and then gate material is provided in the first trenches as in step (b), and said insulating material is removed from the second trenches, and then said second trenches are filled with said deposited semiconductor material of the second conductivity type as in step (c).

20. A method as claimed in

claim 19

, wherein an insulating material suitable for said insulating overlayers on top of the gate material is provided having second windows at said second trenches, said second windows are enlarged in said suitable insulating material after step (c) to expose said source regions while leaving said suitable insulating material to provide said insulating overlayers on top of the gate material, and then said source electrode is provided in said enlarged windows and on said insulating overlayers.

21. A method as claimed in any one of

claims 15

to

19

, wherein the first and second trenches are formed so that each said second trench extends the same depth into the drain region as the first trench surrounding that second trench.

22. A method as claimed in

claim 21

, wherein, after filling the second trenches with said deposited semiconductor material of the second conductivity type, dopant from said deposited semiconductor material is diffused out of said second trenches such that each said localised region will include an out-diffused region of said dopant extending from the side and bottom of the respective second trench.

23. A method as claimed in any one of

claims 15

to

19

, wherein, before filling the second trenches with said deposited semiconductor material of the second conductivity type, dopant ions of the first conductivity type are implanted in the drain region at the bottom of the second trench for providing an avalanche-breakdown region of the first conductivity type that has a higher doping concentration than the adjacent portion of the drain region, thereby determining an avalanche breakdown voltage for the p-n junction that said deposited semiconductor material of the second conductivity type forms therewith at the bottom of the second trench.