UNIVERSAL LOGIC CHIP

• US 20010043081A1
• Filed: 06/04/1999
• Published: 11/22/2001
• Est. Priority Date: 06/08/1998
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: REES, DAVID B.
• Granted Patent: US 6,496,033 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22

Abstract

An integrated circuit or chip having a number of bond pads or inputs that may or may not have a bond wire connecting the pad to a supply voltage, ground or via a package pin to an external input when the chip is placed in the package. The circuits such as the input buffer connected to the pad are normally biased in the opposite voltage to that which the bond wire may be connected. For example, the input buffer circuitry connected to the bond pad, may see the pad as being connected to ground if the bond wires are connected, otherwise the input buffer circuitry will see the pad as being connected to VCC. When the pad is connected to a package pin then the end user may apply an electrical signal (e.g., supply voltage or ground) so that the integrated circuit may be configured as any one of a number of possible devices having one of a set of electrical attributes. Typically, the chip will have up to 8 such pads which can be used individually or in combination to configure the device. In one example, the chip would be part of an existing ‘family’ of chips which all have, for example, N package pins. The extra package pins used to configure the chip would be added to one or both ends of the package so that the rest of the package looks like a normal non-configurable member of the ‘family’.

Claims

1. A method for selecting or determining a function or attribute of an integrated circuit or chip having a plurality of selectable functions and/or attributes comprising the steps of:

providing the integrated circuit or chip with a plurality of pins corresponding to said plurality of selectable functions and/or attributes; and

applying a high or low voltage to each of the plurality of pins to select or determine the function of the chip in response to the voltage applied to each of said pins.

2. A method for selecting or determining a function or attribute of an integrated circuit or chip having a plurality of selectable functions and/or attributes comprising the steps of:

adding a plurality of extra pins and/or bond pads at one or more ends of a package and/or chip; and

applying a high or low voltage to each of the extra pins/pads to select three or more characteristics selected from the group consisting of;

(A) a drive strength of an output buffer,

(B) a threshold level of an input buffer,

(C) an operating voltage of the chip,

(D) enable/disable of a synchronous data transfer,

(E) enable/disable of a register,

(F) the speed of an output buffer,

(G) the noise sensitivity,

(H) whether or not the pins of the device have bus hold features,

(I) the operating speed,

(J) the ground bounce/sensitivity of the output buffers,

(K) the number of I/Os,

(L) the number of data input and/or output pads,

(M) the directionality of data and/or address I/Os (e.g., one-directional or bi-directional),

(N) whether or not the data is inverted,

(O) the number of control pins,

(P) whether some data pads are used or unused, and

(Q) other functions or attributes of the device.

3. A method for selecting or determining a function or attribute of an integrated circuit or chip having a plurality of selectable functions and/or attributes comprising the steps of:

applying a high or low voltage to each of a number of pins on the chip to select three or more characteristics selected from the group consisting of;

(A) a drive strength of an output buffer,

(B) a threshold level of an input buffer,

(C) an operating voltage of the chip,

(D) enable/disable of a synchronous data transfer,

(E) enable/disable of a register,

(F) the speed of an output buffer,

(G) the noise sensitivity of the input buffers,

(H) whether or not the pins of the device have bus hold features,

(I) the operating speed,

(J) the ground bounce/sensitivity of the output buffers,

(K) the number of I/Os,

(L) the number of data input and/or output pads,

(M) the directionality of data and/or address I/Os (e.g., one-directional or bi-directional),

(N) whether or not the data is inverted,

(O) the number of control pins,

(P) whether some data pads are used or unused, and

(Q) other functions or attributes of the device.

4. A circuit comprising:

a first portion configured to provide one of a plurality of functions in response to one or more configuration inputs; and

a second portion configured to receive a high or low voltage at one or more pins to generate said plurality of configuration inputs.

5. The circuit according to

claim 4

, wherein said second portion is connected to a number of bond pads located on an integrated circuit.

6. The circuit according to

claim 4

, wherein said plurality of functions include three or more functions selected from the group consisting of:

(A) a drive strength of an output buffer,

(B) a threshold level of an input buffer,

(C) an operating voltage of the chip,

(D) enable/disable of a synchronous data transfer,

(E) enable/disable of a register,

(F) the speed of an output buffer,

(G) the noise sensitivity,

(H) whether or not the pins of the device have bus hold features,

(I) the operating speed,

(J) the ground bounce/sensitivity of the output buffers,

(K) the number of I/Os,

(L) the number of data input and/or output pads,

(M) the directionality of data and/or address I/Os (e.g., one-directional or bi-directional),

(N) whether or not the data is inverted,

(O) the number of control pins,

(P) whether some data pads are used or unused, and

(Q) other functions or attributes of the device.

7. The circuit according to

claim 5

, wherein a number of bond pads are on the circuit and one or more extra configuration bond pads for configuration are at the ends of the circuit.

8. The circuit according to

claim 7

, wherein the extra configuration bond pads are biased to a voltage on the chip such that an input buffer connected to the configuration bond pad sees a defined logical ‘

1’

or ‘

0’

state.

9. The circuit according to

claim 7

, wherein the extra configuration bond pads may be bonded to a defined logical ‘

1’

or ‘

0’

voltage within the package so as to force an input buffer connected to the pad to see a ‘

1’

or ‘

0’

irrespective of the biasing.

10. The circuit according to

claim 7

, wherein the extra configuration bond pads may be bonded to pins on a package which are extra and are at the ends of the package.

11. The circuit according to

claim 7

, wherein the number of extra configuration bond pads needed on the chip depends on the number of different function/attributes implemented.

12. The circuit according to

claim 10

, wherein the number of extra package pins needed depends on the number of different function/attributes that can be chosen.

13. The circuit according to

claim 7

, wherein:

one or more of the configuration bond pads are biased to a first state or a second state inside the package or on the chip;

one or more of the configuration bond pads are connected to extra package pins so that an externally applied signal voltage can force a ‘

1’

or ‘

0’

on an input buffer connected to the pads.