MULTI-LAYER SWITCHING APPARATUS AND METHOD

• US 20010043614A1
• Filed: 07/17/1998
• Published: 11/22/2001
• Est. Priority Date: 07/17/1998
• Status: Active Grant

• Current Assignee: Sonus Networks Incorporated (Ribbon Communications, Inc.)
• Original Assignee: Network Equipment Technologies Incorporated (Ribbon Communications, Inc.)
• Inventors: VEERINA, MAHESH, VISWANADHAM, KRISHNA
• Granted Patent: US 6,424,659 B2
• Time in Patent Office: Days
• US Class Current: 370/469
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

Multilayer switching device and associated technique enables simultaneous wire-speed routing at OSI layer 3, wire-speed switching at layer 2, and support multiple interfaces at layer 1. Implementation may be embodied using one or more integrated circuits (ASIC), RISC processor, and software, thereby providing wire-speed performance on interfaces, in various operational modes.

Claims

1. A multi-level switching system comprising:

a first-level switch for packet reception or transmission; and

a second-level switch coupled to the first-level switch for enabling packet communication between the second-level switch and the first-level switch.

2. The system of

claim 1

wherein the first-level switch comprises:

an integrated switch module for effectively enabling multi-layer switching;

a processing module coupled to the integrated switch module;

a memory module coupled to the integrated switch module; and

a network interface module coupled to the integrated switch module.

3. The system of

claim 2

wherein the integrated switch module comprises:

a Layer-2 module for effectively enabling Layer-2 packet switching;

a Layer-3 module for effectively enabling Layer-3 packet routing;

a processor interface module for interfacing to the processing module;

a memory interface module for interfacing to the memory module; and

a data path module.

4. The system of

claim 3

wherein the Layer-3 module comprises:

a forwarding module for effectively enabling packet forwarding.

5. The system of

claim 3

wherein the Layer-3 module comprises:

a look-up module for accessing a hash table.

6. The system of

claim 5

wherein the look-up module further modifies a packet.

7. The system of

claim 5

wherein the look-up module further modifies an age flag in an aging table.

8. The system of

claim 5

wherein the look-up module further manages a packet queue.

9. The system of

claim 5

wherein the look-up module further processes packet attributes.

10. The system of

claim 3

wherein the datapath module comprises:

a buffer scheduler module for scheduling a pipeline buffer.

11. The system of

claim 2

wherein the network interface module comprises:

an arbiter module for effectively enabling channel arbitration for packet reception or transmission.

12. The system of

claim 2

wherein the network interface module comprises:

a Local Area Network (LAN) bus controller for coupling to a LAN bus.

13. The system of

claim 3

wherein the memory interface module comprises:

a Direct Memory Access (DMA) module for effectively enabling DMA access to the memory module.

14. The system of

claim 2

wherein the memory module comprises:

a Content Addressable Memory (CAM) module.

15. The system of

claim 2

wherein the memory module comprises:

a local memory, a control memory, a cache memory, or a packet memory.

16. The system of

claim 2

wherein the integrated switch module comprises:

an integrated single-chip circuit for effectively enabling packet traffic broadcasting.

17. The system of

claim 1

wherein the second-level switch comprises:

a cross-bar switch coupled to a multi-protocol router;

the first-level switch being coupled to one or more hubs.

18. Integrated network switching circuit comprising:

a Layer-2 networking element for packet reception or transmission; and

a Layer-3 networking element coupled to the Layer-2 networking element for multi-layer packet switching;

wherein the Layer-3 networking element further comprises;

a forwarding module for effectively enabling packet forwarding;

a look-up module for accessing a hash table, modifying a packet and an age flag in an aging table, managing a packet queue, or processing packet attributes.

19. The circuit of

claim 18

further comprising a network interface comprising:

an arbiter module for arbitrating packet reception or transmission; and

a Local Area Network (LAN) bus controller for coupling to a LAN bus.

20. The circuit of

claim 18

further comprising a memory circuit comprising:

a Content Addressable Memory (CAM);

a local memory;

a control memory;

a cache memory;

or

a packet memory.

21. The circuit of

claim 20

wherein the memory circuit further comprises:

a Direct Memory Access (DMA) circuit for DMA access to the memory circuit.

22. In a network for coupling a first link to a second link, a method for multi-layer packet switching comprising the steps of:

receiving a packet from a first link;

arbitrating the received packet;

managing a packet queue,

accessing a hash table and an age flag in an aging table;

forwarding the received packet according to Layer-2 or Layer-3 switching to a second link.