Semiconductor device and manufacture thereof

• US 20010044199A1
• Filed: 04/20/2001
• Published: 11/22/2001
• Est. Priority Date: 01/05/1998
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Miyai, Yoichi
• Application Number:
  US09/838,923
• Publication Number:
  US 20010044199A1
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

Method and system of interconnecting conductive elements includes forming a lower conductive element (14) having a lower contact section (22) with a width (24) not more than substantially that of an adjacent section (26) of the lower conductive element (14). A first insulation layer (18) may be formed outwardly of the lower conductive element (14). An upper conductive element (16) may be formed outwardly of the first insulation layer (18). The upper conductive element (16) may have a upper contact section (28) with a width (30) not more than substantially that of an adjacent section (32) of the upper conductive element (16). A second insulation layer (20) may be formed outwardly of the first insulation layer (18) and the upper conductive element (16). A contact hold (40) may be formed in the first and second insulation layers (18, 20) exposing a lower contact area (42) of the lower contact section (22) and an upper contact area (44) of the upper contact section (28). An interconnect (54) may be formed in the contact hole (40) connecting the contact areas (42, 44) of the lower and upper conductive elements (14, 16). The interconnect (54) may have a substantially uniform width (56) between the lower and upper conductive elements (14, 16).

Claims

1. A method of interconnecting conductive elements of an integrated circuit, comprising the steps of:

forming a lower conductive element having a lower contact section with a width not more than substantially that of an adjacent section of the lower conductive element;

forming a first insulation layer outwardly of the lower conductive element;

forming an upper conductive element outwardly of the first insulation layer, the upper conductive element having an upper contact section with a width not more than substantially that of an adjacent section of the upper conductive element;

forming a second insulation layer outwardly of the first insulation layer and the upper conductive element;

forming a contact hole in the first and second insulation layers exposing a lower contact area of the lower contact section and an upper contact area of the upper contact section; and

forming an interconnect in the contact hole connecting the contact areas of the lower and upper conductive elements, the interconnect having a substantially uniform width between the lower and upper conductive elements.

2. The method of

claim 1

, wherein the lower contact section is substantially uniform in width to the adjacent section of the lower conductive element and the upper contact section is substantially uniform in width to the adjacent section of the upper conductive element.

3. The method of

claim 1

, wherein the contact area of at least one of the conductive elements substantially comprises a sidewall of the conductive element.

4. The method of

claim 1

, wherein the lower contact area substantially comprises a top of the lower conductive element and the upper contact area substantially comprises a sidewall of the upper conductive element.

5. The method of

claim 1

, wherein the lower contact section is uniform in width to the adjacent section of the lower conductive element and the upper contact section is uniform in width to the adjacent section of the upper conductive element.

6. The method of

claim 1

, wherein the contact hole exposes a top of the lower conductive element and a sidewall of the upper conductive element.

7. The method of

claim 1

, wherein the contact hole exposes a top of the lower conductive element and a sidewall of the upper conductive element, the step of forming the interconnect further comprising the steps of;

depositing a conductive material in the contact hole;

etching away an excess portion of the conductive material deposited in an upper portion of the contact hole; and

forming an interconnect insulator in the upper portion of the contact hole.

8. The method of

claim 1

, wherein the contact sections of the lower and upper conductive elements are non overlapping.

9. The method of

claim 1

, wherein at least one of the contact sections at least partially overlaps the other contact section.

10. The method of

claim 1

, wherein the contact section of at least one of the conductive elements is horizontally displaced from the adjacent section of the conductive element to at least partially overlap the contact section of the other conductive element.

11. The method of

claim 1

, further comprising the steps of;

prior to forming a contact hole, forming an over upper conductive element outwardly of the second insulation layer, the over upper conductive element having an over upper contact section with a width not more than substantially that of an adjacent section of the over upper conductive element;

forming a third insulation layer outwardly of the second insulation layer and the over upper conductive element;

the step of forming the contact hole comprising forming the contact hole in the first, second and third insulation layers exposing a lower contact area of the lower contact section, an upper contact area of the upper contact section and an over upper contact area of the over upper contact section; and

the step of forming the interconnect comprising forming an interconnect in the contact hole connecting the contact areas of the lower, upper and over upper conductive elements, the interconnect having a substantially uniform width between the lower and upper conductive elements and between the upper and over upper conductive elements.

12. A method of fabricating a memory device, comprising the steps of:

forming a first active region on a substrate, the first active region having a first contact section with a width not more than substantially that of an adjacent section of the first active region;

forming a second active region on the substrate, the second active region having a second contact section with a width not more than substantially that of an adjacent section of the second active region;

forming a first insulation layer outwardly of the first and second active regions and the substrate;

forming an upper conductive element outwardly of the first insulation layer, the upper conductive element having an upper contact section with a width not more than substantially that of an adjacent section of the upper conductive element;

forming a second insulation layer outwardly of the first insulation layer and the upper conductive element;

forming a first contact hole in the first and second insulation layers exposing a first contact area of the first contact section and a first upper contact area of the upper contact section;

forming a second contact hole in the first and second insulation layers exposing a second contact area of the second contact section and a second upper contact area of the upper contact section;

forming a first interconnect in the first contact hole connecting the first contact area of the first active region and the first upper contact area of the upper conductive element, the first interconnect having a substantially uniform width between the first active region and the upper conductive element; and

forming a second interconnect in the second contact hole connecting the second contact area of the second active region and the second upper contact area of the upper conductive element, the second interconnect having a substantially uniform width between the second active region and the upper conductive element.

13. The method of

claim 12

, wherein the first contact area substantially comprises a top of the first active region, the second contact area substantially comprises a top of the second active region and the upper contact areas each substantially comprise a sidewall of the upper conductive element.

14. The method of

claim 12

, wherein the first contact section is uniform in width to the adjacent section of the first active region, the second contact section is uniform in width to the adjacent section of the second active region and the upper contact section is uniform in width to the adjacent section of the upper conductive element.

15. The method of

claim 12

, wherein the contact sections of the active regions and the conductive element are non overlapping.

16. The method of

claim 12

, wherein the active regions comprise storage nodes of a DRAM cell array and the conductive element comprises a bit line of the DRAM cell array.

17. An integrated circuit, comprising:

a first conductive element having a first contact section with a width not more than substantially that of an adjacent section of the first conductive element;

a second conductive element having a second contact section with a width not more than substantially that of an adjacent section of the second conductive element;

an insulation layer disposed between the first and second conductive elements; and

an interconnect connecting the contact sections of the first and second conductive elements, the interconnect having a substantially uniform width between the first and second conductive elements.

18. The integrated circuit of

claim 17

, wherein the first contact section is substantially uniform in width to the adjacent section of the first conductive element and the second contact section is substantially uniform in width to the adjacent section of the second conductive element.

19. The integrated circuit of

claim 17

, wherein the contact sections of the conductive elements are non overlapping, the first contact section further comprising a first contact area on a top of the first conductive element and the second contact section further comprising a second contact area on a sidewall of the second conductive element.

20. The integrated circuit of

claim 17

, further comprising;

a third conductive element having a third contact section with a width not more than substantially that of an adjacent section of the third conductive element;

a second insulation layer disposed between the second and third conductive elements; and

the interconnect connecting the contact sections of the first, second and third conductive elements, the interconnect having a substantially uniform width between the first and second conductive elements and between the second and third conductive elements.