Interdigitated capacitor design for integrated circuit lead frames

• US 20010045631A1
• Filed: 06/29/2001
• Published: 11/29/2001
• Est. Priority Date: 04/01/1998
• Status: Active Grant

• Current Assignee: Larry D. Kinsman
• Original Assignee: Larry D. Kinsman
• Inventors: Kinsman, Larry D.
• Granted Patent: US 6,396,134 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49589 Capacitor integral with or on the leadframe
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor device includes a two-part, coplanar, interdigitated decoupling capacitor formed as a part of the conductive lead frame. For down-bonded dice, the die attach paddle is formed as the interdigitated member. Alternatively, an interdigitated capacitor may be placed as a LOC type lead frame member between electrical bond pads on the die. The capacitor sections comprise Vcc and Vss bus bars.

Claims

1. A semiconductor device assembly, comprising:

a semiconductor die having a plurality of circuits formed thereon, having an active surface, having a plurality of bond pads on said active surface, and having an opposing back side;

a lead frame including a plurality of inner leads extending over a first plane, at least one lead of the plurality of inner leads corresponding to a bond pad of said plurality of bond pads of said semiconductor die, a plurality of outer leads, at least one outer lead of said plurality of outer leads connected to at least one inner lead of said plurality of inner leads, and a bifurcated die mounting member including a pair of generally coplanar interdigitated sectors extending over a second plane different from said first plane; and

at least one conductive wire connecting at least one bond pad of said plurality of bond pads of said semiconductor die to at least one corresponding inner lead of said plurality of inner leads of said lead frame..

2. The semiconductor device assembly of

claim 1

, wherein said semiconductor die is adhesively connected to said bifurcated die mounting member.

3. The semiconductor device assembly of

claim 2

, wherein said semiconductor die and said bifurcated die mounting member are adhesively connected to an insulative member located therebetween.

4. The semiconductor device assembly of

claim 1

, further comprising:

a first electrical connection from one of said pair of generally coplanar interdigitated sectors to a power supply Vss bond pad of said plurality of bond pads of said semiconductor die.

5. The semiconductor device assembly of

claim 4

, further comprising:

a second electrical connection from the other of said pair of generally coplanar interdigitated sectors to a ground Vcc bond pad of said plurality of bond pads of said semiconductor die.

6. The semiconductor device assembly of

claim 1

, further comprising

conductive wires connecting said plurality of bond pads and said at least one corresponding inner lead of said plurality of inner leads.

7. The semiconductor device assembly of

claim 1

, wherein said lead frame comprises a single conductive layer.

8. The semiconductor device assembly of

claim 1

, wherein said lead frame comprises a single layer of metal stamped to form said plurality of inner leads, said plurality of outer leads, and said bifurcated die mounting member.

9. The semiconductor device assembly of

claim 1

, wherein said lead frame comprises a single conductive layer fixed to an insulative base layer.

10. The semiconductor device assembly of

claim 1

, wherein said bifurcated die mounting member comprises a two-part paddle for attachment to the back side of said semiconductor die.

11. The semiconductor device assembly of

claim 10

, wherein said bifurcated die mounting member is adhesively attached to said semiconductor die.

12. The semiconductor device assembly of

claim 1

, wherein said bifurcated die mounting member comprises a lead-on-chip (LOC) member for attachment to the active surface of said semiconductor die.

13. The semiconductor device assembly of

claim 12

, wherein said bifurcated die mounting member is adhesively attached to the active surface of said semiconductor die having an intervening insulative layer therebetween.

14. A semiconductor device assembly, comprising:

a semiconductor die having a plurality of circuits formed thereon, having an active surface, having a plurality of bond pads on said active surface, and having an opposing back side;

a lead frame including a plurality of inner leads extending over a first plane, at least one lead of the plurality of inner leads corresponding to at least one bond pad of said plurality of bond pads of said semiconductor die, a plurality of outer leads, at least one outer lead of said plurality of outer leads connected to at least one inner lead of said plurality of inner leads, and a bifurcated die mounting member including a pair of generally coplanar interdigitated sectors extending over a second plane different from said first plane;

an insulative member adhesively connected to said semiconductor die and said bifurcated die mounting member;

a first electrical connection from one of said pair of generally coplanar interdigitated sectors to a power supply Vss bond pad;

a second electrical connection from the other of said pair of generally coplanar interdigitated sectors to a ground Vcc bond pad; and

at least one conductive wire connecting said at least one bond pad of said plurality of bond pads to said at least one inner lead of said plurality of inner leads; and

a plurality of conductive wires connecting said plurality of bond pads and said at least one inner lead of said plurality of inner leads.

15. The semiconductor device assembly of

claim 14

, wherein said lead frame comprises a single conductive layer.

16. The semiconductor device assembly of

claim 14

, wherein said lead frame comprises a single layer of metal stamped to form said plurality of inner leads, said plurality of outer leads, and said bifurcated die mounting member.

17. The semiconductor device assembly of

claim 14

, wherein said lead frame comprises a single conductive layer fixed to said insulative member wherein said insulative member includes a base layer.

18. The semiconductor device assembly of

claim 14

, wherein said bifurcated die mounting member comprises a two-part paddle for attachment to the back side of said semiconductor die.

19. The semiconductor device assembly of

claim 14

, wherein said bifurcated die mounting member comprises a lead-on-chip (LOC) member for attachment to the active surface of said semiconductor die.

20. The semiconductor device assembly of

claim 19

, wherein said bifurcated die mounting member is attached to said insulative member that is attached to the active surface of said semiconductor die.

21. A conductive lead frame strip for a semiconductor device, comprising a strip of polymeric film having a conductive layer, lateral rails, and a plurality of spaced lead frames wherein each lead frame of said plurality of spaced lead frames includes a pattern of a plurality of conductive inner leads and a plurality of conductive outer leads and a die support member bifurcated into two interdigitated capacitor portions, said portions comprising a decoupling capacitor, said two interdigitated capacitor portions are generally coplanar, configured for bonding to a semiconductor die, and configured for wire bond connections to Vss and Vcc bond pads of a semiconductor die, respectively.

22. The conductive lead frame strip of

claim 21

, wherein said bifurcated die support member is generally centrally positioned in said each lead frame of the plurality of lead frames.

23. A method for producing a lead frame including an inductance decoupling capacitor for a semiconductor device using a strip of metallized polymeric film, said method comprising:

removing portions of said metallized polymeric film to form a plurality of patterns in said strip including a pair of opposed side rails, each pattern of said plurality of patterns including a plurality of inner and outer leads supportively connected to said pair of opposed side rails and two separated, interdigitated die attach members, said two separated interdigitated die attach members configured to be a decoupling capacitor couple, said removing portions of said metallized polymeric film to form said plurality of patterns in said strip including said pair of opposed side rails, said each pattern of said plurality of patterns including said plurality of inner and outer leads supportively connected to said pair of opposed side rails and said two separated interdigitated die attach members comprises forming a pattern including two coplanar, separated, and interdigitated die attach members.

24. A method for producing a semiconductor device assembly having an inductance decoupling capacitor formed from a strip of metallized polymeric film, comprising:

removing portions of said metallized polymeric film to form a plurality of patterns in said strip including a pair of opposed side rails, each pattern of said plurality of patterns including a plurality of inner leads and a plurality of outer leads supportively connected by bars to said pair of opposed side rails and at least two separated interdigitated die attach members supportively connected to said pair of opposed side rails by paddle bars, said at least two separated interdigitated die attach members configured to be a decoupling capacitor couple;

providing a semiconductor die having an active surface and a back side, and a plurality of bond pads on said active surface, a first portion of said plurality of bond pads configured to be conductively connected to a power supply, a second portion of said plurality of bond pads configured to be conductively connected to ground, and a third portion of said plurality of bond pads configured to be connected to said plurality of inner leads;

securing said semiconductor die to said at least two separated interdigitated die attach members;

connecting one of said at least two separated interdigitated die attach members to said first portion of said plurality of bond pads; and

connecting the other of said at least two separated interdigitated die attach members to said second portion of said plurality of bond pads; and

attaching said at least two separated interdigitated die attach members to said first and second portions, respectively, of said plurality of bond pads by conductive wires.

25. The method of

claim 24

, wherein said attaching said at least two separated interdigitated die attach members to said first and second portions, respectively, of said plurality of bond pads by said conductive wires comprises bonding said conductive wires by one of thermocompression, thermosonic bonding and ultrasonic bonding.

26. The method of

claim 24

, further comprising:

attaching said third portion of said plurality of bond pads to at least one of said plurality of inner leads.

27. The method of

claim 24

, further comprising:

singulating said plurality of inner leads and said plurality of outer leads from said pair of opposed side rails.

28. The method of

claim 27

, wherein said singulating includes cutting said paddle bars.

29. The method of

claim 24

, further comprising:

singulating said at least two separated interdigitated die attach members from said pair of opposed side rails by said cutting said paddle bars.

30. The method of

claim 24

, wherein said securing said semiconductor die to said at least two separated interdigitated die attach members comprises attaching the back side of said semiconductor die to said at least two separated interdigitated die attach members using an adhesive.

31. The method of

claim 30

, wherein said attaching the back side of said semiconductor die to said at least two separated interdigitated die attach members comprises attaching said back side of said semiconductor die to said at least two separated interdigitated die attach members using polymeric tape and adhesive.

32. The method of

claim 30

, wherein said attaching the back side of said semiconductor die to said at least two separated interdigitated die attach members comprises attaching said back side of said semiconductor die to said at least two separated interdigitated die attach members using insulative polymeric adhesive.

33. The method of

claim 32

, further comprising attaching a portion of said active surface of said semiconductor die to said at least one inner lead of said plurality of inner leads using an insulative layer.

34. The method of

claim 32

, wherein said attaching the back side of said semiconductor die to said at least two separated interdigitated die attach members comprises attaching said back side of said semiconductor die to said at least two separated interdigitated die attach members using said polymeric tape and adhesive.