Power wiring structure and semiconductor device

• US 20010045639A1
• Filed: 05/16/2001
• Published: 11/29/2001
• Est. Priority Date: 05/25/2000
• Status: Active Grant

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: Hanamura, Akihiro
• Granted Patent: US 6,501,167 B2
• Time in Patent Office: Days
• US Class Current: 257/691
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A power wiring structure realizes low inductance and is applicable to a semiconductor device.

The power wiring structure employs two switching elements that are connected in series and are complementarily turned on and off. Ends of the switching elements are connected to power lines extending from a power source. A node between the switching elements is connected to an output line U that is connected to load. The power lines are a high-potential power line P and a low-potential power line N. The lines P, N, and U are each a wide electrode with the width thereof greater than the thickness thereof. The electrodes are layered one upon another in a thickness direction in order of P, U, and N to form a three-layer wide electrode structure.

A current of the same value as and oppositely oriented from a current flowing through the output line U flows through the output line P or N, to cancel magnetic fields generated by the currents, thereby effectively reducing wiring inductance.

Claims

1. A power wiring structure comprising a circuit containing a first power line, a second power line, and an output line to load, the first power line being connected to a high-potential power source, the second power line being connected to a low-potential power source, the circuit being connected to first and second switching elements that are connected in series and are complementarily turned on and off, a node between the first and second switching elements being connected to the output line, wherein:

the first power line, second power line, and output line are each a wide electrode with the width thereof greater than the thickness thereof; and

the first power line, second power line, and output line are layered one upon another in a thickness direction in order of the first power line, output line, and second power line with an insulator interposed between adjacent ones of the layered lines.

2. The power wiring structure of

claim 1

, wherein:

the output line includes a plurality of lines of different phases, output ends of these lines being collected and layered one upon another between the first and second power lines.

3. A semiconductor device comprising:

a power wiring structure including a first power line, a second power line, and an output line, these lines being each a wide electrode with the width thereof greater than the thickness thereof and being layered one upon another in order of the first power line, output line, and second power line with an insulator interposed between adjacent ones of the layered lines;

a first conductive layer selectively formed on a first insulating substrate;

a first semiconductor chip formed on the first conductive layer, having a bottom electrode electrically connected to the first conductive layer;

a second conductive layer selectively formed on a second insulating substrate;

a second semiconductor chip formed on the second conductive layer, having a bottom electrode electrically connected to the second conductive layer;

means for electrically connecting the first conductive layer to the first power line;

means for electrically connecting a top electrode of the first semiconductor chip to the output line;

means for electrically connecting a top electrode of the second semiconductor chip to the second power line; and

means for electrically connecting the second conductive layer to the output line.

4. The semiconductor device of

claim 3

, wherein:

the first and second insulating substrates are arranged on each side of the power wiring structure.

5. The semiconductor device of

claim 3

, wherein:

the first and second insulating substrates are arranged on each side of the power wiring structure; and

the power wiring structure is inclined to substantially equalize the heights of wiring connection points between the first and second insulating substrates.

6. The semiconductor device of

claim 3

, wherein:

the first and second insulating substrates are arranged side by side on one side of the power wiring structure along the length of the power wiring structure.

7. The semiconductor device of any one of

claims 3

to

6

, wherein:

each of the semiconductor chips includes a switching element and a free wheeling diode;

the switching element and free wheeling diode are arranged side by side along the length of the power wiring structure; and

the conductive layer for each semiconductor chip is separated into two, one for a bottom electrode of the switching element and another for a bottom electrode of the free wheeling diode.

8. The semiconductor device of any one of

claims 3

to

6

, wherein:

each of the semiconductor chips includes a switching element and a free wheeling diode; and

the switching element and free wheeling diode are arranged along a line that is orthogonal to the length of the power wiring structure.

9. The semiconductor device of any one of

claims 3

to

8

, wherein the electrically connecting means are bonding wires.

10. The semiconductor device of

claim 9

, wherein the bonding wires connected to the bottom electrode of any one of the semiconductor chips and the bonding wires connected to the top of the semiconductor chip extend in the same direction.

11. The semiconductor device of any one of

claims 3

to

10

, wherein the first and second insulating substrates are integrated into a common substrate.