Gray scale pixel driver for electronic display and method of operation therefor

• US 20010045929A1
• Filed: 01/22/2001
• Published: 11/29/2001
• Est. Priority Date: 01/21/2000
• Status: Active Grant

• Current Assignee: eMagin Corporation (Samsung Electronics Co. Ltd.)
• Original Assignee: eMagin Corporation (Samsung Electronics Co. Ltd.)
• Inventors: Malaviya, Shashi D., Prache, Olivier F.
• Granted Patent: US 6,809,710 B2
• Time in Patent Office: Days
• US Class Current: 345/89
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0866 by means of changes in the pixel supply voltage
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2310/0259 with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• CPC Class Codes: G09G 2310/066 Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

A circuit is disclosed for driving an OLED in a graphics display. The circuit employs a current source operating in a switched mode. The output of the current source is connected to a terminal of the OLED. The current source is responsive to a combination of a selectively set cyclical voltage signal and a cyclical variable amplitude voltage signal. The current source, when switched on, is designed and optimized to supply the OLED with the amount of current necessary for the OLED to achieve maximum luminance. When switched off, the current source blocks the supply of current to the OLED, providing a uniform black level for an OLED display. The apparent luminance of the OLED is controlled by modulating the pulse width of the current supplied to the OLED, thus varying the length of time during which current is supplied to the OLED. By using a switched mode of operation at the current source, the circuit of the present invention is able to employ a larger range of voltages to control the luminance values in a current-driven OLED display.

Claims

1. A circuit for driving a light emitting diode in a display using a current supply, said circuit comprising:

a first transistor having a source, a drain, and a gate;

a current supply connected to the first transistor source;

an anode terminal of a light emitting diode connected to the first transistor drain; and

a means for applying a combination of at least two voltages to the first transistor gate so as to control the time that the current supply is connected to the light emitting diode.

2. The circuit of

claim 1

wherein said means for applying comprises:

a second transistor having a source, a drain, and a gate, said second transistor drain being connected to the first transistor gate;

a first voltage source connected to the second transistor gate;

a second voltage source connected to the second transistor source;

a capacitor having first and second terminals, said first capacitor terminal being connected to the first transistor gate; and

a third voltage source connected to the second capacitor terminal.

3. The circuit of

claim 2

wherein the second voltage source is adapted to selectively vary output voltage periodically, and the third voltage source is adapted to provide a cyclical voltage ramp.

4. The circuit of

claim 2

wherein the display comprises a plurality of driving circuits and wherein said third voltage source is connected to each of said driving circuits.

5. The circuit of

claim 2

wherein the first and second transistors comprise P-type devices.

6. The circuit of

claim 1

wherein said means for applying comprises:

second and third transistors, each having a source, a drain, and a gate;

a first voltage source connected to the second transistor gate;

a second voltage source connected to the second transistor source and the third transistor drain;

a third voltage source connected to the third transistor gate;

a capacitor having first and second terminals;

a fourth voltage source connected to the first capacitor terminal; and

a node connected to the second transistor drain, the third transistor source, the second capacitor terminal, and the first transistor gate.

7. The circuit of

claim 6

wherein the second voltage source is adapted to selectively vary output voltage periodically, and the fourth voltage source is adapted to provide a cyclical voltage ramp.

8. The circuit of

claim 6

wherein the display comprises a plurality of driving circuits and wherein said fourth voltage source is connected to each of said driving circuits.

9. The circuit of

claim 6

wherein the first and second transistors comprise P-type devices, and the third transistor comprises an N-type device.

10. The circuit of

claim 1

wherein said means for applying comprises:

second, third, fourth, and fifth transistors, each having a source, a drain, and a gate;

a first voltage source connected to the second transistor gate;

a second voltage source connected to the second transistor source and the third transistor drain;

a third voltage source connected to the third transistor gate;

a fourth voltage source connected to the fourth transistor gate;

a fifth voltage source connected to the fifth transistor gate;

a first node connected to the second transistor drain, the third transistor source, the fourth transistor source, and the fifth transistor drain;

a capacitor having first and second terminals;

a sixth voltage source connected to the first capacitor terminal; and

a second node connected to the fourth transistor drain, the fifth transistor source, the second capacitor terminal, and the first transistor gate.

11. The circuit of

claim 10

wherein the second voltage source is adapted to selectively vary output voltage periodically, and the sixth voltage source is adapted to provide a cyclical voltage ramp.

12. The circuit of

claim 10

wherein the display comprises a plurality of driving circuits and wherein said sixth voltage source is connected to each of said driving circuits.

13. The circuit of

claim 10

wherein the first, second, and fourth transistors comprise P-type devices, and the third and fifth transistors comprise N-type devices.

14. The circuit of

claim 1

wherein said at least two voltages comprise:

a data voltage; and

a ramp voltage.

15. The circuit of

claim 1

wherein the means for applying comprises:

a data voltage source;

a capacitor having first and second terminals;

a display row access subcircuit operatively connecting the data voltage source and the capacitor first terminal; and

a ramp voltage source operatively connected to the capacitor second terminal.

16. The circuit of

claim 15

wherein the display row access subcircuit comprises at least one transistor.

17. The circuit of

claim 15

wherein the display row access subcircuit comprises at least two transistors.

18. The circuit of

claim 1

wherein the means for applying comprises:

a data voltage source;

a capacitor having first and second terminals;

a display row access subcircuit and a display column access subcircuit connected in series and operatively connecting the data voltage source with the capacitor first terminal; and

a ramp voltage source operatively connected to the capacitor second terminal.

19. The circuit of

claim 18

wherein the display row access subcircuit comprises at least two transistors, and the display column access subcircuit comprises at least two transistors.

20. The circuit of

claim 1

further comprising:

a node coupled to the first transistor drain and the light emitting diode anode terminal; and

a test transistor having a drain and a gate connected to said node, and having a source connected to ground.

21. The circuit of

claim 20

wherein the means for applying comprises:

a data voltage source;

a capacitor having first and second terminals;

a display row access subcircuit operatively connecting the data voltage source and the capacitor first terminal; and

a ramp voltage source operatively connected to the capacitor second terminal.

22. The circuit of

claim 21

wherein the display row access subcircuit comprises at least one transistor.

23. The circuit of

claim 1

wherein said means for applying comprises:

second, third, fourth, and fifth transistors, each having a source, a drain, and a gate;

a first voltage source connected to the second transistor gate;

a second voltage source connected to the second transistor source and the third transistor drain;

a third voltage source connected to the third transistor gate;

a fourth voltage source connected to the fourth transistor gate;

a fifth voltage source connected to the fifth transistor gate;

a first node connected to the second transistor drain, the third transistor source, the fourth transistor source, and the fifth transistor drain;

a capacitor having first and second terminals;

a sixth voltage source connected to the first capacitor terminal; and

a second node connected to the fourth transistor drain, the fifth transistor source, the second capacitor terminal, and the first transistor gate, and wherein the circuit further comprises;

a third node coupled to the first transistor drain and the light emitting diode anode terminal;

a sixth transistor having a drain and a gate connected to said third node, and having a source connected to ground;

a seventh voltage source; and

a seventh transistor having a source connected to the third node, a drain connected to the second voltage source, and a gate connected to the seventh voltage source.

24. The circuit of

claim 23

wherein the second voltage source is adapted to selectively vary output voltage periodically, and the sixth voltage source is adapted to provide a cyclical voltage ramp.

25. The circuit of

claim 23

wherein the display comprises a plurality of driving circuits and wherein said sixth voltage source is connected to each of said driving circuits.

26. The circuit of

claim 23

wherein the first, second, fourth, sixth, and seventh transistors comprise P-type devices, and the third and fifth transistors comprise N-type devices.

27. A method of driving a light emitting diode in a display using a current supply, said method comprising the steps of:

applying current to an OLED responsive to at least one power transistor being in a turned on state;

turning on at least one access transistor responsive to a cyclical voltage;

applying a DATA voltage to a node responsive to the access transistor being turned on, said node being connected to at least the access transistor, a capacitor, and the at least one power transistor;

charging the capacitor responsive to the application of the DATA voltage to the node;

turning off the at least one access transistor so as to discontinue charging the capacitor in response to the DATA voltage;

applying a cyclical variable amplitude voltage to the capacitor;

further charging the capacitor responsive to the application of the cyclical variable amplitude voltage to the capacitor; and

turning the at least one power transistor off responsive to the voltage at the node so as to selectively control the current supplied to the OLED from a current source.

28. A method of driving a light emitting diode in a display using a current supply, said method comprising the steps of:

applying current to an OLED responsive to at least one power transistor being in a turned on state;

selectively turning the at least one power transistor off responsive to a power transistor gate voltage comprised of the combination of a selectively set cyclical DATA voltage and a cyclical variable amplitude RAMP voltage.

29. A current supply control circuit, comprising:

a switch, the switch having a control input, a current source input, and a current supply output, the switch providing current at the current supply output in response to the voltage level at the control input crossing a threshold level;

a current supply, the current supply coupled to the current source input of the switch;

a first voltage source, the first voltage source being coupled to the control input of the switch, the first voltage source supplying a periodic variable-level voltage signal, the periodic variable-level voltage signal exceeding the threshold level of the switch for a time period; and

a second voltage source, the second voltage source being coupled to the control input of the switch, the second voltage source supplying a substantially level voltage signal, the signal provided to the control input of the switch and combined with the voltage signal from the first voltage source, whereby the time period during which the resulting voltage signal exceeds the threshold level of the switch is varied in accordance with the voltage from the second voltage source.

30. The circuit of

claim 29

, wherein the switch is a transistor having a source, a drain, and a gate.

31. The circuit of

claim 29

, wherein the current supply control circuit is adapted to couple to the anode of a light emitting diode.

32. The current supply control circuit of

claim 29

, wherein the first voltage source and the second voltage source are provided to a combination circuit before being provided to the control input.

33. The current supply control circuit of

claim 32

, wherein the combination circuit comprises:

a first transistor having a source, a drain, and a gate, the first transistor drain being connected to the control input of the switch, and the first transistor source being connected to the second voltage source;

a third voltage source, the third voltage source being connected to the first transistor gate; and

a capacitor, the capacitor having a first terminal and a second terminal, the first capacitor terminal being connected to the control input of the switch, and the second capacitor terminal being connected to the first voltage source.

34. A method for controlling the operation of a current switch wherein the current switch is responsive to a control voltage crossing a threshold level, the method comprising:

providing a first voltage signal as the control voltage of the current switch, the first voltage signal exceeding the threshold level of the switch for a first time period;

adding a second voltage signal to the first voltage signal, whereby the resultant voltage signal is offset from the first voltage signal; and

providing the resultant voltage signal as the control voltage of the current switch, whereby the resultant voltage exceeds the threshold level of the switch for a second time period, whereby the difference between the first time period and the second time period is dependent on the second voltage signal.

35. The method of

claim 34

, wherein the current switch is a transistor.

36. The method of

claim 35

, wherein the control voltage is the gate voltage of the transistor.

37. The method of

claim 34

, wherein the first voltage signal is a ramp signal.

38. The method of

claim 34

, wherein the second voltage signal is a level voltage signal.

39. The method of

claim 34

, further comprising providing the second voltage signal to a memory module and adding the first voltage to the memory module.

40. The method of

claim 38

, wherein the memory module is a capacitor.