LOW LATENCY SHARED MEMORY SWITCH ARCHITECTURE

• US 20010046235A1
• Filed: 12/30/1999
• Published: 11/29/2001
• Est. Priority Date: 09/11/1996
• Status: Active Grant

• Current Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Original Assignee: David Book, Robert Hale Grant, Stephen Trevitt
• Inventors: TREVITT, STEPHEN, GRANT, ROBERT HALE, BOOK, DAVID
• Granted Patent: US 6,510,161 B2
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/108 using shared central buffer
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/608 ATM switches adapted to switch variable length packets, e.g. IP packets
• CPC Class Codes: H04Q 11/0421 Circuit arrangements therefor

Abstract

A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Claims

1. A method for operating a time slicing shared memory switch, comprising the acts of:

receiving a plurality of data frames in a respective plurality of input channels to said switch;

applying said plurality of data frames to a shared memory in a time sliced manner, wherein a time slice for each section of a shared memory is staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of said data frames to said memory and on a next clock cycle said one memory portion is accessed for reading at least a portion of said data from said memory.

2. A method for reducing a data path latency and an inter-frame delay associated with time slicing shared memory switches, comprising the acts of:

receiving a respective plurality of data frames;

receiving locations of memory partitions associated with said plurality of data frames;

identifying memory partitions as a function of a time slice number;

applying corresponding ones of said data frames to respective memory partitions identified by the time slice number, wherein data is applied to said partitions in a time sliced manner, and wherein a time slice for each section of a shared memory is staggered so that on any clock cycle, one memory partition is being accessed for writing of at least one of said data frames and on a next clock cycle said one memory portion may be accessed for reading at least a portion of said data from said memory.

3. An apparatus for reducing a data path latency and an inter-frame delay associated with time slicing shared memory switches, comprising:

a bus for receiving a plurality of data frames in a respective plurality of input channels to said switch; and

a slice crosspoint for applying said plurality of data frames to a shared memory in a time sliced manner, wherein a time slice for each section of a shared memory is staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of said data frames to said memory and on a next clock cycle said one memory portion is accessed for reading at least a portion of said data from said memory.

4. A shared memory switch, comprising:

a bus for receiving a plurality of data frames in a respective plurality of input channels to said switch;

a slice crosspoint for applying said plurality of data frames to a shared memory in a time sliced manner, wherein a time slice for each section of a shared memory is staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of said data frames to said memory and on a next clock cycle said one memory portion is accessed for reading at least a portion of said data from said memory.

5. The apparatus of

claim 4

wherein said shared memory switch follows a Fibre Channel protocol.

6. Apparatus for reducing a data path latency and an inter-frame delay of a time slicing shared memory switch, comprising:

a plurality of memory write data buses for receiving a respective plurality of data frames;

a plurality of memory write address busses for supplying locations of memory partitions associated with said plurality of data frames;

a address slice crosspoint for generating a time slice number for identifying memory partitions identified by portions of the addresses received from said memory write address busses;

and a data slice crosspoint for applying corresponding ones of said data frames to respective memory partitions identified by a corresponding time slice number generated by said address slice crosspoint, wherein data is applied to said partitions in a time sliced manner, and wherein a time slice for each section of a shared memory is staggered so that on any clock cycle, one memory partition is being accessed for writing of at least one of said data frames and on a next clock cycle said one memory portion may be accessed for reading at least a portion of said data from said memory.

7. The apparatus of

claim 6

wherein said time slicing shared memory switch follows a Fibre Channel protocol.

8. The apparatus of

claim 6

wherein said time slicing shared memory switch is a 16 port switch.

9. The apparatus of

claim 6

wherein said time slicing shared memory switch is 32 bits wide.

10. The apparatus of

claim 6

wherein said memory partitions are 16 in number.