xDSL communications systems using shared/multi-function task blocks
First Claim
Patent Images
1. A communications system comprising:
- a digital data buffer circuit for storing digital data, said digital data including both receive data and transmit data; and
a shared signal processing circuit for performing a set of signal processing operations on both said receive data and said transmit data, said shared signal processing circuit having computing resources shared by a receive task and a transmit task; and
said computing resources including a set of independent application specific (ASIC) logic circuits interconnected by a local bus and using a common clock, said set of independent ASIC logic circuits including at least one multi-tasking ASIC logic circuit, and which multi-tasking ASIC logic circuit during a single period of said common clock selectively performs either a first signal processing operation on said receive data and/or a second signal processing operation on said transmit data.
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Abstract
A communications system includes a shared signal processing circuit for performing a set of signal processing operations on both receive data and said transmit data. The signal processing circuit is also shared by a plurality of communications ports. To further enhance operation of the system, the computing resources include a set of independent application specific (ASIC) logic circuits, with at least some of the ASICs selectively performing either a first signal processing operation and/or a second signal processing operation on data in response to control information embedded in an input data object.
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Citations
36 Claims
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1. A communications system comprising:
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a digital data buffer circuit for storing digital data, said digital data including both receive data and transmit data; and
a shared signal processing circuit for performing a set of signal processing operations on both said receive data and said transmit data, said shared signal processing circuit having computing resources shared by a receive task and a transmit task; and
said computing resources including a set of independent application specific (ASIC) logic circuits interconnected by a local bus and using a common clock, said set of independent ASIC logic circuits including at least one multi-tasking ASIC logic circuit, and which multi-tasking ASIC logic circuit during a single period of said common clock selectively performs either a first signal processing operation on said receive data and/or a second signal processing operation on said transmit data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A communications system for controlling a plurality of separate data transmissions for an associated plurality of separate communications ports, the system comprising:
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a digital data buffer circuit for storing digital data, such that each of the plurality of separate communications ports includes an associated port-specific digital data buffer for storing port-specific digital data; and
a shared signal processing circuit for performing a set of signal processing operations on said port-specific digital data to extract a port-specific data stream, said shared signal processing circuit having computing resources shared by the plurality of separate communications ports; and
said computing resources including a set of application specific (ASIC) logic circuits interconnected by a local bus and using a common clock, said ASIC logic circuits including at least one multi-tasking ASIC logic circuit, which multi-tasking ASIC logic circuit selectively performs either a first or a second signal processing operation on said port-specific digital data during a period of said common clock;
wherein said first signal processing operation is associated with a first communication port of said plurality of separate communications port, and said second signal processing operation is associated with a second communication port of said plurality of separate communications port. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A digital subscriber loop (DSL) communications system for performing data transmissions for a plurality of independent communications ports, the DSL communications system comprising:
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a digital data buffer circuit for storing discrete multi-tone (DMT) symbols, said DMT symbols including both receive DMT symbols and transmit DMT symbols for each communication port from the plurality of independent communications ports; and
a shared signal processing circuit for performing a set of signal processing operations on both said receive DMT symbols and transmit DMT symbols for each communication port from the plurality of independent communications ports, said set of signal processing operations including both transmission convergence operations and physical medium dependent operations supporting an xDSL protocol standard in the data transmissions; and
said shared signal processing circuit including a set of application specific (ASIC) logic circuits using a common clock, each ASIC logic circuit being configured to perform a single signal processing operation associated with a receive DMT symbol or a transmit DMT symbol during a single period of said common clock; and
said set of ASIC logic circuits further including at least one multi-tasking ASIC logic circuit, which multi-tasking ASIC logic circuit performs at least two signal processing operations, such that during a during a single period of said common clock said multi-tasking ASIC logic circuit is selectively controlled to perform either a first type of signal processing operation on a receive DMT symbol or a second type of signal processing operation on transmit DMT symbol;
wherein said first type of signal processing operation and second type of signal processing operation can be performed for each communication port from the plurality of independent communications ports, such that during any single period of said common clock said set of ASIC logic circuits is simultaneously processing a plurality of DMT symbols for the plurality of communications ports. - View Dependent Claims (17, 18, 19, 20)
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21. A method of operating a communications system comprising the steps of:
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(a) performing a set of receive operations for a receive task on a received data signal in accordance with a transmission protocol to extract a received data stream, wherein said set of receive operations is performed for more than one communication port in a plurality of communication ports used in the communications system; and
(b) performing a set of transmit operations for a transmit task to generate a transmit data signal based on a transmit data stream, wherein said set of transmit operations is also performed for more than one communication port in said plurality of communication ports used in the communications system; and
(c) using a signal processing circuit for performing both step (a) and step (b), said signal processing circuit including at least one set of computing circuits that are each coupled to a single common local bus for exchanging results associated with steps (a) and (b);
wherein said at least one set of computing circuits performs at least some of both said set of receive operations and at least some of said set of transmit operations so that such at least one set of computing circuits is shared by more than one communication port and is further shared by said receive task and said transmit task. - View Dependent Claims (22, 23, 24)
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25. A method of operating a communications system comprising the steps of:
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buffering receive digital data to be processed in a data receive path; and
buffering transmit digital data already processed in a data transmit path; and
performing a first set of signal processing operations on both said receive digital data and said transmit digital data using a using an interconnected set of independent application specific (ASIC) logic circuits coupled to a common bus; and
clocking said interconnected set of independent application specific (ASIC) logic circuits with a common clock; and
using at least a first ASIC logic circuit from said interconnected set of independent application specific (ASIC) logic circuits in a multi-tasking capacity such that during a single period of said common clock, said first ASIC logic circuit selectively performs either a first signal processing operation for said data receive path and/or a second signal processing operation for said data transmit path. - View Dependent Claims (26, 27, 28)
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29. A method of performing data transmissions for a plurality of independent communications ports in a digital subscriber loop (DSL) communications system the method comprising the steps of:
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(a) storing discrete multi-tone (DMT symbols, said DMT symbols including both receive DMT symbols and transmit DMT symbols for each communication port from the plurality of independent communications ports; and
(b) providing computing resources in the form of a set of application specific (ASIC) logic circuits including;
1) one or more single task application specific (ASIC) logic circuits using a common clock, each single task ASIC logic circuit being configured to perform a single signal processing operation associated with a receive DMT symbol or a transmit DMT symbol during a single period of said common clock; and
2) at least one multi-tasking ASIC logic circuit coupled to said set of ASIC logic circuits, which multi-tasking ASIC logic circuit performs at least two signal processing operations, such that during a during a single period of said common clock said multi-tasking ASIC logic circuit is selectively controlled to perform either a first type of signal processing operation on a receive DMT symbol or a second type of signal processing operation on transmit DMT symbol;
(c) performing a set of signal processing operations on both said receive DMT symbols and transmit DMT symbols for each communication port from the plurality of independent communications ports using said set of ASIC logic circuits, said set of signal processing operations including both transmission convergence operations and physical medium dependent operations supporting an xDSL protocol standard in the data transmissions; and
wherein said first type of signal processing operation and second type of signal processing operation can be performed for each communication port from the plurality of independent communications ports, such that during any single period of said common clock said set of ASIC logic circuits is simultaneously processing a plurality of DMT symbols for the plurality of communications ports. - View Dependent Claims (30, 31, 32)
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33. A method of operating a multi-port communications system using an xDSL signaling protocol, the method comprising the steps of:
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(a) providing a processing pipeline for performing physical medium dependent operations and transport convergence operations for a number of communications port based on the xDSL signaling protocol; and
(b) using a first portion of said processing pipeline for performing a first set of signal processing operations for each communications port from said number of communications port, said first portion of said processing pipeline including a first set of one or more shared ASIC computing circuits, said first set of one or more shared ASIC computing circuits being used for a transmission operation and a receive operation for said number of communications ports; and
(c) using a second portion of said processing pipeline for performing a second set of signal processing operations for each communications port from said number of communications port, said second portion of said processing pipeline including a second set of one or more shared ASIC computing circuits, said second set of one or more shared ASIC computing circuits also being used for a transmission operation and a receive operation for said number of communications ports; and
(d) using a third portion of said processing pipeline for performing a third set of signal processing operations for each communications port from said number of communications port, said third portion of said processing pipeline including a general purpose programmable processor used for a transmission operation and a receive operation for said number of communications ports; and
wherein said first, second and third portions of said processing pipeline use a common pipeline clock. - View Dependent Claims (34, 35, 36)
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Specification