Serial bus system
First Claim
Patent Images
1. A serial bus system comprising:
- a bus master; and
at least one bus slave, connected to the bus master via at least one bus line, the bus system being operable in a normal mode in which, at the latest after a normal cycle time has elapsed, the bus master transmits digital signals to the at least one bus slave, and the at least one bus slave transmits digital signals back to the bus master after each such transmission, with each of the transmitted digital signals being interpreted as a logic zero when a first predetermined current waveform is applied to the bus line, and being interpreted as a logic one when a second predetermined current waveform, which is different to the first predetermined current waveform, is applied to the bus line, and operable in an energy saving mode in which the bus master does not transmit any digital signals to the at least one bus slave within the normal cycle time.
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Abstract
Two measures are provided in order to allow a serial bus system to be operated such that it is resistant to interference and defects, and such that it operates with low power consumption. Firstly, each transmitted digital signal is interpreted as a logic zero or a logic one, respectively, when a first or a second predetermined current waveform, respectively, is applied to a bus line. Secondly, the bus system is operable in an energy saving mode, in which either no data transmissions at all are made, or in which data transmissions are made only rarely, between the individual bus modules.
11 Citations
17 Claims
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1. A serial bus system comprising:
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a bus master; and
at least one bus slave, connected to the bus master via at least one bus line, the bus system being operable in a normal mode in which, at the latest after a normal cycle time has elapsed, the bus master transmits digital signals to the at least one bus slave, and the at least one bus slave transmits digital signals back to the bus master after each such transmission, with each of the transmitted digital signals being interpreted as a logic zero when a first predetermined current waveform is applied to the bus line, and being interpreted as a logic one when a second predetermined current waveform, which is different to the first predetermined current waveform, is applied to the bus line, and operable in an energy saving mode in which the bus master does not transmit any digital signals to the at least one bus slave within the normal cycle time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification
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Current AssigneeTranspacific Silica LLC (Intellectual Ventures LLC)
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Original AssigneeSiemens AG
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InventorsIndefrey, Klaus, Wiesgickl, Bernhard
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current713/320
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CPC Class CodesH04L 12/12 Arrangements for remote con...H04L 12/403 with centralised control, e...H04L 2012/40254 Actuator Sensor Interface ASIY02D 30/50 in wire-line communication ...
